Util Extract#

clkdata_indata_in_triggerdata_validdata_outvalid_outtrigger_oututil_extract

The Util Extract core allows the extraction of the trigger signal and restoration of the data signal that was embedded in the data stream by the AXI ADC Trigger.

Files#

Name

Description

library/util_extract/util_extract.v

Verilog source for the peripheral.

Configuration Parameters#

Name

Description

Default Value

Choices/Range

NUM_OF_CHANNELS

Number of channels

2

DATA_WIDTH

Data width. It assumes the trigger is in bit (n*16)-1, with n being the channel number

32

Interface#

Physical Port

Logical Port

Direction

Dependency

clk CLK

in

Physical Port

Direction

Dependency

Description

data_in

in [31:0]

Input data from the FIFO. Will replace each trigger bit with the sign extended version of the data. It should be data from the output of the variable fifo

data_in_trigger

in [31:0]

Data from which the trigger is extracted. It should be data from the input of the variable fifo

data_valid

in

Valid for the input data

data_out

out [31:0]

Data without the embedded trigger

valid_out

out

Valid for the output data

trigger_out

out

Trigger output. Is an logic OR of the triggers from all the channels that are captured simulaneously