Util VAR FIFO#

The Util VAR FIFO core controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering.

Features#

  • Variable depth

Files#

Name

Description

library/util_var_fifo/util_var_fifo.v

Verilog source for the peripheral.

Configuration Parameters#

Name

Description

Default Value

Choices/Range

DATA_WIDTH

Data width of the FIFO. The BRAM generator parameters should match this.

32

ADDRESS_WIDTH

The BRAM generator parameters should match this. Gives the maximum depth of the FIFO

13

Interface#

Physical Port

Logical Port

Direction

Dependency

clk CLK

in

Physical Port

Logical Port

Direction

Dependency

rst RST

in

Physical Port

Direction

Dependency

Description

depth

in [31:0]

Controls the depth of the FIFO. Should be less than the maximum depth. Controlled by an outside IP.

data_in

in [31:0]

Data to be stored.

data_in_valid

in

Valid for the input data.

data_out

out [31:0]

Data forwarded to the DMA.

data_out_valid

out

Valid for the output data.

wea_w

out

Write signal.

en_w

out

Write enable signal.

addr_w

out [12:0]

Address for the write pointer.

din_w

out [31:0]

Data to be written to the BRAM.

en_r

out

Read enable signal.

addr_r

out [12:0]

Address for the read pointer.

dout_r

in [31:0]

Data read from the BRAM.

Detailed Description#

This IP controls an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.

Design Guidelines#

The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It uses only one clock domain, so everything should be synchronous to that clock domain.