AD7134-FMC HDL project#

Overview#

The AD7134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC), based on the continuous time sigma-delta (CTSD) modulation scheme. The CTSD architecture inherently rejects signals around the ADC aliasing frequency band, giving the device its inherent antialiasing capability, and removes the need for a complex external antialiasing filter.

The device has four independent converter channels in parallel, each with a CTSD modulator and a digital decimation and filtering path. The bandwidth of each ADC channel ranges from dc to 391.5 kHz, making the device an ideal candidate for universal precision data acquisition solutions supporting a breadth of sensor types, from temperature and pressure to vibration and shock.

It supports a wide range of ODR frequencies, from 0.01 kSPS to 1496 kSPS with less than 0.01 SPS adjustment resolution, allowing the user to granularly vary sampling speed to achieve coherent sampling. The adc offers three main digital filter profile options: a wideband low ripple filter (2.5 kSPS to 374 kSPS), a fast responding sinc3 filter (0.01 kSPS to 1496 kSPS), and a balanced sinc6 filter with an ODR range 2.5 kSPS to 1.496 MSPS.

The AD7134 supports two device configuration schemes: serial peripheral interface (SPI) and hardware pin configuration (pin control mode). The SPI control mode offers access to all the features and configuration options available on the chip. Pin control mode offers the benefit of simplifying the device configuration, enabling the device to operate autonomously after power -up operating in a standalone mode. In addition to the optional SPI, it has a flexible and independent data interface for transmitting the ADC output data.

The EVAL-AD7134FMCZ evaluation kit features the AD7134 24-bit, 4-channel, simultaneous sampling adc. Two on-board AD7134 ADCs are included to demonstrate multidevice simultaneous sampling. The HDL reference design provides all the interfaces necessary to interact with the device using a Xilinx FPGA development board.

Supported boards#

EVAL-AD7134FMCZ

Supported devices#

AD7134

Supported carriers#

ZedBoard on FMC slot *

Legend

* FMC extender needed for connecting the EVAL board

Block design#

The reference design uses the SPI Engine Framework to interface with the two AD7134 ADCs. It only supports the slave mode for both devices with both DCLK and ODR generated by the FPGA. Each device sends data on 4 of the 8 DIN bits.

Block diagram#

The data path and clock domains are depicted in the diagram below:

Multidevice Synchronization#

An important feature that is specific to this project is multidevice synchronization. The single low speed ODR line makes it easy to synchronize the devices by providing less than 10 ns of phase matching between channels on different devices.

Applications such as condition-based monitoring, power quality analyzer, and sonar system require tight phase matching across a large numbers of channels, making the digital interface design complex. To achieve tight synchronization, the user must configure all the devices in slave mode and use the SPI to set a specific register to reset the digital interface before the data capture. This command must be given to all the slaves simultaneously using one single SPI write command.

From the HDL perspective, this means driving both CS lines at the same time and sending the same data to both ADCs. The CS signals are only connected when the user wants to write in a specific register to achieve multidevice synchronization.

Jumper setup#

Jumper/Solder link	Position	Description
JP14	Mounted	DEC0/DCLKIO (Device 1) [DCLK Input]
JP15	Mounted	DEC0/DCLKIO (Device 2) [DCLK Input]
JP16	Mounted	MODE (Device 1) [Slave Mode]
JP17	Mounted	MODE (Device 2) [Slave Mode]

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at HDL Architecture).

Instance	Address
dual_ad7134_axi_regmap	0x44A0_0000
axi_ad7134_dma	0x44A3_0000
odr_generator	0x44B0_0000
axi_ad7134_clkgen	0x44B1_0000

SPI connections#

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	AD7134	0
PS	SPI 0	AD7134	1

GPIOs#

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
ad713x_dclkmode	INOUT	49	103
ad713x_pinbspi	INOUT	48	102
ad713x_dclkio[1:0]	INOUT	47:46	101:100
ad713x_gpio[7:0]	INOUT	45:38	99:92
ad713x_mode[1:0]	INOUT	37:36	91:90
ad713x_pdn[1:0]	INOUT	35:34	89:88
ad713x_resetn[1:0]	INOUT	33:32	87:86

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ad7134_dma	13	57	89
dual_ad7134	12	56	88

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

user@analog:~$ cd hdl/projects/ad7134_fmc/zed
user@analog:~/hdl/projects/ad7134_fmc/zed$ make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources#

HDL related#

AD7134-FMC HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	here
AXI_DMAC	library/axi_dmac	here
AXI_HDMI_TX	library/axi_hdmi_tx	here
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	here
AXI_SDDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	here
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	here
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	here
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	here
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	here
AXI_SYSID_ROM	library/sysid_rom	here
UTIL_I2C_MIXER	library/util_i2c_mixer	—

SPI Engine Framework documentation

More information#

ADI HDL User guide

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.