AD9213-EVB HDL project

Overview

The AD9213-EVB reference design is a processor based (e.g. Microblaze) embedded system.

The design implements a high-speed receive chain using JESD204B.

The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a buffer implemented on block rams from the FPGA fabric (util_adcfifo).

All cores from the receive chain are programmable through an AXI-Lite interface.

Supported boards

• AD9213-EVB

Supported devices

• AD9213

Supported carriers

Evaluation board	Carrier	FMC slot
AD9213-EVB	VCU118	FMC+

Block design

Block diagram

The data path and clock domains are depicted in the below diagrams:

Important

The Rx links (ADC Path) operate with the following parameters:

• Rx parameters: L=16, M=1, F=2, S=16, NP=16, N=16

• Sample Rate: 10 GSPS

• Dual link: No

• RX_DEVICE_CLK: 312.25 MHz (Lane Rate/40)

• REF_CLK: 625 MHz (Lane Rate/20)

• JESD204B Lane Rate: 12.5 Gbps

• QPLL0

\[Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{10}{8}\]

Clock scheme

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Check-out the table below to find out the conditions.

Instance	Zynq/Microblaze
axi_ad9213_xcvr	0x44A6_0000
rx_ad9213_tpl_core	0x44A1_0000
axi_ad9213_jesd	0x44A9_0000
axi_ad9213_dma	0x7C42_0000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	spi0	axi_spi	0
PL	hmc7044_spi	HMC7044	0
		ADF4371	1

GPIOs

GPIO signal	Direction	HDL GPIO EMIO
	(from FPGA view)
rstb	OUT	38
hmc_sync_req	OUT	37
gpio[4:0]	INOUT	36:32

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	IRQ number
hmc7044_spi	5
axi_ad9213_dma	12
axi_ad9213_jesd	13

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the projects/ad9213_evb location and run the make command by typing in your command prompt:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9213_evb/vcu118

~/hdl/projects/ad9213_evb/vcu118$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Hardware related

• Product datasheet: AD9213

• Device data sheet

• Evaluation Board

HDL related

• AD9213_EVB HDL project source code

IP name	Source code link	Documentation link
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_ADXCVR	library/xilinx/util_adxcvr	UTIL_ADXCVR core for AMD Xilinx devices
AXI_ADXCVR	library/xilinx/axi_adxcvr	AMD Xilinx Devices
AXI_JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
JESD204_TPL_ADC	library/jesd204/ad_ip_jesd204_tpl_adc	ADC JESD204B/C Transport Peripheral

• [Wiki] Generic JESD204B block designs

• JESD204 Interface Framework

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.