ADRV904x HDL reference design

The ADRV904x is a highly integrated, system on chip (SoC) radio frequency (RF) agile transceiver with integrated digital front end (DFE). The SoC contains eight transmitters, two observation receivers for monitoring transmitter channels, eight receivers, integrated LO and clock synthesizers, and digital signal processing functions. The SoC meets the high radio performance and low power consumption demanded by cellular infrastructure applications including small cell basestation radios, macro 3G/4G/5G systems, and massive MIMO base stations.

Supported devices

Supported boards

Supported carriers

Evaluation board

Carrier

FMC slot

EVAL-ADRV904x

ZCU102

FMC HPC0

VCK190

FMCP1

Block design

Block diagram

The data path and clock domains are depicted in the below diagrams:

Configuration modes

The block design supports configuration of parameters and scales.

We have listed a couple of examples at section Building the HDL project and the default modes for each project.

Note

The parameters for Rx or Tx links can be changed from the system_project.tcl file, located in hdl/projects/adrv904x/$CARRIER/system_project.tcl

\[Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{66}{64}\]

The following are the parameters of this project that can be configured:

  • JESD_MODE: used link layer encoder mode

    • 64B66B - 64b66b link layer defined in JESD204C

    • 8B10B - 8b10b link layer defined in JESD204B

  • RX_LANE_RATE: lane rate of the Rx link

  • TX_LANE_RATE: lane rate of the Tx link

  • [RX/TX]_JESD_M: number of converters per link

  • [RX/TX]_JESD_L: number of lanes per link

  • [RX/TX]_JESD_S: number of samples per frame

  • [RX/TX]_JESD_NP: number of bits per sample

  • [RX/TX]_NUM_LINKS: number of links

Clock scheme

ADRV904x ZCU102 clock scheme

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

ZynqMP

Versal

axi_adrv904x_tx_jesd

0x84A9_0000

0xA4A9_0000

axi_adrv904x_rx_jesd

0x84AA_0000

0xA4AA_0000

axi_adrv904x_tx_dma

0x9C42_0000

0xBC42_0000

axi_adrv904x_rx_dma

0x9C40_0000

0xBC40_0000

tx_adrv904x_tpl_core

0x84A0_4000

0xA4A0_4000

rx_adrv904x_tpl_core

0x84A0_0000

0xA4A0_0000

axi_adrv904x_tx_xcvr

0x84A8_0000

0xA4A8_0000

axi_adrv904x_rx_xcvr

0x84A6_0000

0xA4A6_0000

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PS

spi0

ADRV904x

0

AD9528

1

GPIOs

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq MP

ad9528_reset_b

INOUT

69

147

ad9528_sysref_req

INOUT

68

146

adrv904x_trx0_enable

INOUT

67

145

adrv904x_trx1_enable

INOUT

66

144

adrv904x_trx2_enable

INOUT

65

143

adrv904x_trx3_enable

INOUT

64

142

adrv904x_trx4_enable

INOUT

63

141

adrv904x_trx5_enable

INOUT

62

140

adrv904x_trx6_enable

INOUT

61

139

adrv904x_trx7_enable

INOUT

60

138

adrv904x_orx0_enable

INOUT

59

137

adrv904x_orx1_enable

INOUT

58

136

adrv904x_test

INOUT

57

135

adrv904x_reset_b

INOUT

56

134

adrv904x_gpio[0:23]

INOUT

55:32

133:110

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux ZynqMP

Actual ZynqMP

axi_adrv904x_tx_jesd

10

106

138

axi_adrv904x_rx_jesd

11

107

139

axi_adrv904x_tx_dma

13

108

140

axi_adrv904x_rx_dma

14

109

141

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the projects/adrv904x location and run the make command by typing in your command prompt:

Linux/Cygwin/WSL

~$

cd hdl/projects/adrv904x/zcu102

~/hdl/projects/adrv904x/zcu102$

make

The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. Where a cell contains a — (dash) it means that the parameter doesn’t exist for that project (adrv904x/carrier or adrv904x/carrier).

Parameter

Default value of the parameters depending on carrier

ZCU102/VCK190

JESD_MODE

64B66B

RX_LANE_RATE

16.22

TX_LANE_RATE

16.22

RX_JESD_M

16

RX_JESD_L

8

RX_JESD_S

1

TX_JESD_M

16

TX_JESD_L

8

TX_JESD_S

1

A more comprehensive build guide can be found in the Build an HDL project user guide.

Other considerations

ADC - lane mapping

Due to physical constraints, Rx lanes are reordered as described in the following table.

ADC phy Lane

FPGA Rx lane / Logical Lane

0

5

1

6

2

4

3

7

4

2

5

3

6

1

7

0

DAC - lane mapping

Due to physical constraints, Tx lanes are reordered as described in the following table.

DAC phy lane

FPGA Tx lane / Logical lane

0

0

1

1

2

2

3

3

4

7

5

6

6

5

7

4

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.