AXI AD7768#
The AXI AD7768 IP core
can be used to interface the AD7768 and
AD7768-4 ADC, in 1, 2, 4 or 8 data lines active.
More about the generic framework interfacing ADCs, that contains the
up_adc_channel
and up_adc_common modules
, can be read in Generic AXI ADC.
Features#
AXI based configuration
CRC validation flag
Configurable number of active data lines
Real-time data header access
Vivado and Quartus compatible
Files#
Name |
Description |
---|---|
Verilog source for the AXI AD7768. |
|
Verilog source for the AXI AD7768 interface module. |
|
TCL script to generate the Vivado IP-integrator project. |
|
TCL script to generate the Quartus IP-integrator project. |
Block Diagram#
Configuration Parameters#
Name |
Description |
Default Value |
Choices/Range |
---|---|---|---|
ID |
Core ID should be unique for each IP in the system |
0 |
|
NUM_CHANNELS |
Select number of ADC channels. 8 for AD7768 and 4 for AD7768-4 |
8 |
4, 8 |
Interface#
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
s_axi_awaddr |
AWADDR |
in [15:0] |
|
s_axi_awprot |
AWPROT |
in [2:0] |
|
s_axi_awvalid |
AWVALID |
in |
|
s_axi_awready |
AWREADY |
out |
|
s_axi_wdata |
WDATA |
in [31:0] |
|
s_axi_wstrb |
WSTRB |
in [3:0] |
|
s_axi_wvalid |
WVALID |
in |
|
s_axi_wready |
WREADY |
out |
|
s_axi_bresp |
BRESP |
out [1:0] |
|
s_axi_bvalid |
BVALID |
out |
|
s_axi_bready |
BREADY |
in |
|
s_axi_araddr |
ARADDR |
in [15:0] |
|
s_axi_arprot |
ARPROT |
in [2:0] |
|
s_axi_arvalid |
ARVALID |
in |
|
s_axi_arready |
ARREADY |
out |
|
s_axi_rdata |
RDATA |
out [31:0] |
|
s_axi_rresp |
RRESP |
out [1:0] |
|
s_axi_rvalid |
RVALID |
out |
|
s_axi_rready |
RREADY |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
s_axi_aclk |
CLK |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
s_axi_aresetn |
RST |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
adc_clk |
CLK |
out |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
clk_in |
CLK |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
adc_reset |
RST |
out |
Physical Port |
Direction |
Dependency |
Description |
---|---|---|---|
adc_dovf |
in |
Data overflow input, from the DMA. |
|
ready_in |
in |
Input ready signal. |
|
data_in |
in [7:0] |
Serial input data. |
|
adc_sshot |
in |
Single shot conversion. |
|
adc_data |
out [31:0] |
Serial output data. |
|
adc_sync |
out |
Start of transfer flag for serial data. |
|
adc_valid |
out |
Set when valid data is available in the serial output. |
|
adc_crc_ch_mismatch |
out [7:0] |
Channels CRC mismatch flags register. |
|
adc_enable_* |
out |
Set when the channel is enabled, activated by software. |
|
adc_valid_* |
out |
Set when valid channel data is available on the bus. |
|
adc_data_* |
out [31:0] |
Channel parallel output data. |
Detailed Architecture#
Detailed Description#
The top module, axi_ad7768, instantiates:
The ad7768 interface module
The ADC channel register map
The ADC common register map
The AXI handling interface
The AD7768 interface module has as input the serial data lines, the ready_in
signal and the interface clock. Data is deserialized according to the number
of active lanes. The interface module also implements a parallel CRC check
algorithm.
The data from the interface module is processed by the adc channel module.
up_adc_common
module implements the ADC COMMON register map, allowing for
basic monitoring and control of the ADC.
up_adc_channel
module implements the ADC CHANNEL register map, allowing for
basic monitoring and control of the ADC’s channel.
Register Map#
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x0 |
0x0 |
VERSION |
Version and Scratch Registers |
|||
[31:0] |
VERSION |
RO |
0x00000000 |
Version number. Unique to all cores. |
||
0x1 |
0x4 |
ID |
Version and Scratch Registers |
|||
[31:0] |
ID |
RO |
0x00000000 |
Instance identifier number. |
||
0x2 |
0x8 |
SCRATCH |
Version and Scratch Registers |
|||
[31:0] |
SCRATCH |
RW |
0x00000000 |
Scratch register. |
||
0x3 |
0xc |
CONFIG |
Version and Scratch Registers |
|||
[0:0] |
IQCORRECTION_DISABLE |
RO |
0x0 |
If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) |
||
[1:1] |
DCFILTER_DISABLE |
RO |
0x0 |
If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) |
||
[2:2] |
DATAFORMAT_DISABLE |
RO |
0x0 |
If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) |
||
[3:3] |
USERPORTS_DISABLE |
RO |
0x0 |
If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) |
||
[4:4] |
MODE_1R1T |
RO |
0x0 |
If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet) |
||
[5:5] |
DELAY_CONTROL_DISABLE |
RO |
0x0 |
If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) |
||
[6:6] |
DDS_DISABLE |
RO |
0x0 |
If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) |
||
[7:7] |
CMOS_OR_LVDS_N |
RO |
0x0 |
CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) |
||
[8:8] |
PPS_RECEIVER_ENABLE |
RO |
0x0 |
If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) |
||
[9:9] |
SCALECORRECTION_ONLY |
RO |
0x0 |
If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) |
||
[12:12] |
EXT_SYNC |
RO |
0x0 |
If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. |
||
[13:13] |
RD_RAW_DATA |
RO |
0x0 |
If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel. |
||
0x4 |
0x10 |
PPS_IRQ_MASK |
PPS Interrupt mask |
|||
[0:0] |
PPS_IRQ_MASK |
RW |
0x1 |
Mask bit for the 1PPS receiver interrupt |
||
0x7 |
0x1c |
FPGA_INFO |
FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values) |
|||
[31:24] |
FPGA_TECHNOLOGY |
RO |
0x00 |
Encoded value describing the technology/generation of the FPGA device (arria 10/7series) |
||
[23:16] |
FPGA_FAMILY |
RO |
0x00 |
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) |
||
[15:8] |
SPEED_GRADE |
RO |
0x00 |
Encoded value describing the FPGA’s speed-grade |
||
[7:0] |
DEV_PACKAGE |
RO |
0x00 |
Encoded value describing the device package. The package might affect high-speed interfaces |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x10 |
0x40 |
RSTN |
ADC Interface Control & Status |
|||
[2:2] |
CE_N |
RW |
0x0 |
Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables |
||
[1:1] |
MMCM_RSTN |
RW |
0x0 |
MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
||
[0:0] |
RSTN |
RW |
0x0 |
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
||
0x11 |
0x44 |
CNTRL |
ADC Interface Control & Status |
|||
[16:16] |
SDR_DDR_N |
RW |
0x0 |
Interface type (1 represents SDR, 0 represents DDR) |
||
[15:15] |
SYMB_OP |
RW |
0x0 |
Select symbol data format mode (0x1) |
||
[14:14] |
SYMB_8_16B |
RW |
0x0 |
Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) |
||
[12:8] |
NUM_LANES |
RW |
0x00 |
Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported. |
||
[3:3] |
SYNC |
RW |
0x0 |
Initialize synchronization between multiple ADCs |
||
[2:2] |
R1_MODE |
RW |
0x0 |
Select number of RF channels 1 (0x1) or 2 (0x0). |
||
[1:1] |
DDR_EDGESEL |
RW |
0x0 |
Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers. |
||
[0:0] |
PIN_MODE |
RW |
0x0 |
Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge. |
||
0x12 |
0x48 |
CNTRL_2 |
ADC Interface Control & Status |
|||
[1:1] |
EXT_SYNC_ARM |
RW |
0x0 |
Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
[2:2] |
EXT_SYNC_DISARM |
RW |
0x0 |
Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
[8:8] |
MANUAL_SYNC_REQUEST |
RW |
0x0 |
Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
0x13 |
0x4c |
CNTRL_3 |
ADC Interface Control & Status |
|||
[8:8] |
CRC_EN |
RW |
0x0 |
Setting this bit will enable the CRC generation. |
||
[7:0] |
CUSTOM_CONTROL |
RW |
0x00 |
Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode , bit 1 - enables alternate bit polarity decode). |
||
0x15 |
0x54 |
CLK_FREQ |
ADC Interface Control & Status |
|||
[31:0] |
CLK_FREQ |
RO |
0x00000000 |
Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock. |
||
0x16 |
0x58 |
CLK_RATIO |
ADC Interface Control & Status |
|||
[31:0] |
CLK_RATIO |
RO |
0x00000000 |
Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr). |
||
0x17 |
0x5c |
STATUS |
ADC Interface Control & Status |
|||
[4:4] |
ADC_CTRL_STATUS |
RO |
0x0 |
If set, indicates that the device’s register data is available on the data bus. |
||
[3:3] |
PN_ERR |
RO |
0x0 |
If set, indicates pn error in one or more channels. |
||
[2:2] |
PN_OOS |
RO |
0x0 |
If set, indicates pn oos in one or more channels. |
||
[1:1] |
OVER_RANGE |
RO |
0x0 |
If set, indicates over range in one or more channels. |
||
[0:0] |
STATUS |
RO |
0x0 |
Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. |
||
0x18 |
0x60 |
DELAY_CNTRL |
ADC Interface Control & Status(‘’Deprecated from version 9’’) |
|||
[17:17] |
DELAY_SEL |
RW |
0x0 |
Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below. |
||
[16:16] |
DELAY_RWN |
RW |
0x0 |
Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay. |
||
[15:8] |
DELAY_ADDRESS |
RW |
0x00 |
Delay address, the range depends on the interface pins, data pins are usually at the lower range. |
||
[4:0] |
DELAY_WDATA |
RW |
0x00 |
Delay write data, a value of 1 corresponds to (1/200)ns for most devices. |
||
0x19 |
0x64 |
DELAY_STATUS |
ADC Interface Control & Status(‘’Deprecated from version 9’’) |
|||
[9:9] |
DELAY_LOCKED |
RO |
0x0 |
Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements. |
||
[8:8] |
DELAY_STATUS |
RO |
0x0 |
If set, indicates busy status (access pending). The read data may not be valid if this bit is set. |
||
[4:0] |
DELAY_RDATA |
RO |
0x00 |
Delay read data, current delay value in the elements |
||
0x1a |
0x68 |
SYNC_STATUS |
ADC Synchronization Status register |
|||
[0:0] |
ADC_SYNC |
RO |
0x0 |
ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems. |
||
0x1c |
0x70 |
DRP_CNTRL |
ADC Interface Control & Status |
|||
[28:28] |
DRP_RWN |
RW |
0x0 |
DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
||
[27:16] |
DRP_ADDRESS |
RW |
0x000 |
DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
||
[15:0] |
RESERVED |
RO |
0x0000 |
Reserved for backward compatibility. |
||
0x1d |
0x74 |
DRP_STATUS |
ADC Interface Control & Status |
|||
[17:17] |
DRP_LOCKED |
RO |
0x0 |
If set indicates that the DRP has been locked. |
||
[16:16] |
DRP_STATUS |
RO |
0x0 |
If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
||
[15:0] |
RESERVED |
RO |
0x0000 |
Reserved for backward compatibility. |
||
0x1e |
0x78 |
DRP_WDATA |
ADC DRP Write Data |
|||
[15:0] |
DRP_WDATA |
RW |
0x0000 |
DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
||
0x1f |
0x7c |
DRP_RDATA |
ADC DRP Read Data |
|||
[15:0] |
DRP_RDATA |
RO |
0x0000 |
DRP read data (does not include GTX lanes). |
||
0x20 |
0x80 |
ADC_CONFIG_WR |
ADC Write Configuration Data |
|||
[31:0] |
ADC_CONFIG_WR |
RW |
0x00000000 |
Custom Write to the available registers. |
||
0x21 |
0x84 |
ADC_CONFIG_RD |
ADC Read Configuration Data |
|||
[31:0] |
ADC_CONFIG_RD |
RO |
0x00000000 |
Custom read of the available registers. |
||
0x22 |
0x88 |
UI_STATUS |
User Interface Status |
|||
[2:2] |
UI_OVF |
RW1C |
0x0 |
User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. |
||
[1:1] |
UI_UNF |
RW1C |
0x0 |
User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. |
||
[0:0] |
UI_RESERVED |
RW1C |
0x0 |
Reserved for backward compatibility. |
||
0x23 |
0x8c |
ADC_CONFIG_CTRL |
ADC RD/WR configuration |
|||
[31:0] |
ADC_CONFIG_CTRL |
RW |
0x00000000 |
Control RD/WR requests to the device’s register map: bit 1 - RD (‘b1) , WR (‘b0), bit 0 - enable WR/RD operation. |
||
0x28 |
0xa0 |
USR_CNTRL_1 |
ADC Interface Control & Status |
|||
[7:0] |
USR_CHANMAX |
RW |
0x00 |
This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
0x29 |
0xa4 |
ADC_START_CODE |
ADC Synchronization start word |
|||
[31:0] |
ADC_START_CODE |
RW |
0x00000000 |
This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1). |
||
0x2e |
0xb8 |
ADC_GPIO_IN |
ADC GPIO inputs |
|||
[31:0] |
ADC_GPIO_IN |
RO |
0x00000000 |
This reads auxiliary GPI pins of the ADC core |
||
0x2f |
0xbc |
ADC_GPIO_OUT |
ADC GPIO outputs |
|||
[31:0] |
ADC_GPIO_OUT |
RW |
0x00000000 |
This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1). |
||
0x30 |
0xc0 |
PPS_COUNTER |
PPS Counter register |
|||
[31:0] |
PPS_COUNTER |
RO |
0x00000000 |
Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse. |
||
0x31 |
0xc4 |
PPS_STATUS |
PPS Status register |
|||
[0:0] |
PPS_STATUS |
RO |
0x0 |
If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it’s not active. |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x100 + 0x16*n |
0x400 + 0x58*n |
CHAN_CNTRLn |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[11:11] |
ADC_LB_OWR |
RW |
0x0 |
If set, forces ADC_DATA_SEL to 1, enabling data loopback |
||
[10:10] |
ADC_PN_SEL_OWR |
RW |
0x0 |
If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored |
||
[9:9] |
IQCOR_ENB |
RW |
0x0 |
if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
[8:8] |
DCFILT_ENB |
RW |
0x0 |
if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
||
[6:6] |
FORMAT_SIGNEXT |
RW |
0x0 |
if set, enables sign extension (applicable only in 2’s complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). |
||
[5:5] |
FORMAT_TYPE |
RW |
0x0 |
Select offset binary (0x1) or 2’s complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). |
||
[4:4] |
FORMAT_ENABLE |
RW |
0x0 |
Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). |
||
[3:3] |
RESERVED |
RO |
0x0 |
Reserved for backward compatibility. |
||
[2:2] |
RESERVED |
RO |
0x0 |
Reserved for backward compatibility. |
||
[1:1] |
ADC_PN_TYPE_OWR |
RW |
0x0 |
If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored |
||
[0:0] |
ENABLE |
RW |
0x0 |
If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. |
||
0x101 + 0x16*n |
0x404 + 0x58*n |
CHAN_STATUSn |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[12:12] |
CRC_ERR |
RW1C |
0x0 |
CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards. |
||
[11:4] |
STATUS_HEADER |
RO |
0x00 |
The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x). |
||
[2:2] |
PN_ERR |
RW1C |
0x0 |
PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. |
||
[1:1] |
PN_OOS |
RW1C |
0x0 |
PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. |
||
[0:0] |
OVER_RANGE |
RW1C |
0x0 |
If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. |
||
0x102 + 0x16*n |
0x408 + 0x58*n |
CHAN_RAW_DATAn |
ADC Raw Data Reading Where n is from 0 to 15. |
|||
[31:0] |
ADC_READ_DATA |
RO |
0x00000000 |
Raw data read from the ADC. |
||
0x104 + 0x16*n |
0x410 + 0x58*n |
CHAN_CNTRLn_1 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:16] |
DCFILT_OFFSET |
RW |
0x0000 |
DC removal (if equipped) offset. This is a 2’s complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
||
[15:0] |
DCFILT_COEFF |
RW |
0x0000 |
DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
||
0x105 + 0x16*n |
0x414 + 0x58*n |
CHAN_CNTRLn_2 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:16] |
IQCOR_COEFF_1 |
RW |
0x0000 |
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
[15:0] |
IQCOR_COEFF_2 |
RW |
0x0000 |
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
0x106 + 0x16*n |
0x418 + 0x58*n |
CHAN_CNTRLn_3 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[19:16] |
ADC_PN_SEL |
RW |
0x0 |
Selects the PN monitor sequence type (available only if ADC supports it). \ - 0x0: pn9a (device specific, modified pn9) \ - 0x1: pn23a (device specific, modified pn23) \ - 0x4: pn7 (standard O.150) \ - 0x5: pn15 (standard O.150) \ - 0x6: pn23 (standard O.150) \ - 0x7: pn31 (standard O.150) \ - 0x9: pnX (device specific, e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \ |
||
[3:0] |
ADC_DATA_SEL |
RW |
0x0 |
Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC) |
||
0x108 + 0x16*n |
0x420 + 0x58*n |
CHAN_USR_CNTRLn_1 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[25:25] |
USR_DATATYPE_BE |
RO |
0x0 |
The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[24:24] |
USR_DATATYPE_SIGNED |
RO |
0x0 |
The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[23:16] |
USR_DATATYPE_SHIFT |
RO |
0x00 |
The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[15:8] |
USR_DATATYPE_TOTAL_BITS |
RO |
0x00 |
The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[7:0] |
USR_DATATYPE_BITS |
RO |
0x00 |
The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
0x109 + 0x16*n |
0x424 + 0x58*n |
CHAN_USR_CNTRLn_2 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:16] |
USR_DECIMATION_M |
RW |
0x0000 |
This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[15:0] |
USR_DECIMATION_N |
RW |
0x0000 |
This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
0x10a + 0x16*n |
0x428 + 0x58*n |
CHAN_CNTRLn_4 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:3] |
RESERVED |
RO |
0x00000000 |
Reserved for backward compatibility. |
||
[2:0] |
SOFTSPAN |
RW |
0x7 |
Softspan configuration register. |
Design Guidelines#
The control of the AD7768 chip is done through a SPI interface, which is needed at system level.
The ADC interface signals must be connected directly to the top file of the design, as IO primitives are part of the IP.
The example design uses a DMA to move the data from the output of the IP to memory.
If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc interface module (at IP level).
The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module.
Software Support#
Linux documentation on wiki
Linux documentation for AD7768-1 on wiki
No-OS driver at drivers/adc/ad7768, drivers/adc/ad7768-1
No-OS project at projects/ad7768-evb, projects/ad7768-1fmcz
IIO documentation support for AD7768-1 on wiki
References#
HDL IP core at library/axi_ad7768
HDL project at projects/ad7768evb, projects/ad77681evb
HDL project documentation at AD7768-EVB HDL project