ADAQ8092-FMC HDL project

Overview

The EVAL-ADAQ8092 evaluates the ADAQ8092, a 14-bit, 105MSPS , high-speed dual-channel data acquisition uModule solution. This device uses the System-in-Package (SiP) that integrates three common signal processing and conditioning blocks.

This EVAL-ADAQ8092 board does not need an external power supply to operate and requires a very small jitter in the clock source. We recommend to use the DC1075B to improve the clock signal source. For full details on the ADAQ8092, see the ADAQ8092 data sheet, which must be consulted in conjunction with this user guide when using the EVAL-ADAQ8092.

Supported boards

• EVAL-ADAQ8092

• DC1075B

Supported devices

• ADAQ8092

Supported carriers

Evaluation board	Carrier	FMC slot
EVAL-ADAQ8092	ZedBoard	FMC-LPC

Block design

Warning

The VADJ for the Zedboard must be set to 2.5V.

Block diagram

Clock scheme

• External clock source

  • Rohde & Schwarz SMA100A (clock source) - Suggested

  • DC1075B (Clock Divider) - Suggested

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq/Microblaze
axi_adaq8092	0x44A0_0000
axi_adaq8092_dma	0x44A3_0000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	ADAQ8092	0

GPIOs

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO	Software GPIO
	(from FPGA view)		Zynq-7000	Zynq MP
en_1p8	OUT	35	89	113
adc_pd2	OUT	34	88	112
adc_pd1	OUT	33	87	111
adc_par_ser	IN	32	86	110

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_adaq8092_dma	13	57	89

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/adaq8092_fmc/zed

~/hdl/projects/adaq8092_fmc/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Systems related

• [Wiki] ADAQ8092 Evaluation Board User Guide

Hardware related

• Product datasheets: ADAQ8092

HDL related

• EVAL-ADAQ8092 HDL project source code

IP name	Source code link	Documentation link
AXI_ADAQ8092	library/axi_adaq8092	AXI ADAQ8092
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility

Software related

• [Wiki] ADAQ8092 14-Bit, 105 MSPS, μModule Linux device driver

• Python support :

  • ADAQ8092 Python class documentation

  • ADAQ8092 PyADI-IIO example

  • PyADI-IIO documentation

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.