AD738x_FMC HDL project

Overview

The AD7380/ AD7381 are a 16-bit and 14-bit pin-compatible family of dual simultaneous sampling, high speed, low power, successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a 3.3 V power supply and feature throughput rates up to 4 MSPS.The analog input type is differential for the AD7380, AD7381, AD4680, AD4681, AD7380-4, AD7389-4, AD7381-4 can accepts a wide common-mode input voltage, and is sampled and converted on the falling edge of CS.

The AD7383, AD7384, AD4682 and AD4683 have the pseudo-differential input while the AD7386, AD7387, AD7388, AD4684 and AD4685 have single-ended input. The AD7380 family has optional integrated on-chip oversampling blocks to improve dynamic range and reduce noise at lower bandwidths. An internal 2.5 V reference is included. Alternatively, an external reference up to 3.3 V can be used.

The conversion process and data acquisition use standard control inputs allowing for easy interfacing to microprocessors or DSPs. It is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces, using a separate logic supply.

The dual AD7380, AD7381, AD4680, AD4681, AD7383, AD7384, AD4682, AD4683, AD7386, AD7387, AD7388, AD4684 and AD4685 family are available in a 16-lead 3mm x 3mm LFCSP package while the quad generics AD7380-4, AD7389-4, and AD7381-4 are available in 4mmx4mm LFCSP package. Both the duals and quad generic operate in specified from -40°C to +125°C temperature range.

Applications:

• Motor control position feedback

• Motor control current sense

• Data acquisition system

• EDFA applications

• I and Q demodulation

• SONAR

• Power Quality

Supported boards

• EVAL-AD7380FMCZ

• EVAL-AD7381FMCZ

• EVAL-AD7386FMCZ

• EVAL-AD7383FMCZ

• EVAL-AD7380-4FMCZ

Supported devices

• AD7380

• AD7380-4

• AD7381

• AD7381-4

• AD7383

• AD7383-4

• AD7384

• AD7384-4

• AD7386

• AD7387

• AD7388

• AD7388-4

• AD7389-4

• AD4680

• AD4681

• AD4682

• AD4683

• AD4684

• AD4685

Supported carriers

• ZedBoard on FMC slot

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

Configuration modes

The ALERT_SPI_N configuration parameter defines if a known pin will operate as a serial data output pin or alert indication pin. By default it is set to 0. Depending on the required pin functionality, some hardware modifications need to be done on the board and/or make command:

In case of the Serial Data Output Pin functionality:

~$

make ALERT_SPI_N=0

In case of the Alert Indication Output Pin functionality:

~$

make ALERT_SPI_N=1

The NUM_OF_SDI configuration parameter defines the number of SDI lines used: {1, 2, 4}. By default is set to 1.

For the ALERT functionality, the following parameters will be used in make command: ALERT_SPI_N.

For the serial data output functionality, the following parameters will be used in make command: ALERT_SPI_N, NUM_OF_SDI.

Jumper setup

Jumper/Solder link	Default Position	Description
LK1	1	Use internal -2.5 V from U9 for AMP_PWR-
LK2	1	Use internal 5 V from U8 for AMP_PWR+.
LK3	1	Use 12 V power supply from FMC
LK4	3	Use internal +3V3 from U3 for VREF
LK5	3	Use internal 2.3 V from U6 for VLOGIC
JP1	1 (SMD RES)	Connect external SubMiniature Version B (SMB) Connector J1 to the A1 buffer amplifier
JP2	1 (SMD RES)	Connect internal signal from A2 to ADC U10 input AINA-
JP3	1 (SMD RES)	Connect internal signal from A2 to ADC U10 input AINA+
JP4	3 (SMD RES)	The REFIO pin is driven with the external on board reference
JP5	1 (SMD RES)	Use internal +3V3 from U2 for VCC.
JP6	1 (SMD RES)	Connect external SMB Connector J2 to the A1 buffer amplifier

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq
spi_ad738x_adc_axi_regmap	0x44A0_0000
axi_ad738x_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
spi_trigger_gen	0x44B0_0000

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL	iic_main	axi_iic_main	0x4160_0000	—

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	axi_spi_engine	ad738x	0

GPIOs

The Software GPIO number is calculated as follows:

• Zynq-7000: if PS7 is used, then the offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO	Assigned value	Assigned value
	(from FPGA view)		Zynq-7000	ALERT_SPI_N=1	ALERT_SPI_N=0
gpio[33]	OUT	33	87	sdid	0
gpio[32]	OUT	32	86	sdib	0

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ad738x_dma	13	57	89
spi_ad738x_adc	12	56	88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad738x_fmc/zed

~/hdl/projects/ad738x_fmc/zed$

make ALERT_SPI_N=0 NUM_OF_SDI=4

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

make ALERT_SPI_N=0 NUM_OF_SDI=4

then the folder name will be:

ALERTSPIN0_NUMOFSDI4

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Hardware related

• Product datasheets:

  • AD7380

  • AD7380-4

  • AD7381

  • AD7381-4

  • AD7383

  • AD7383-4

  • AD7384

  • AD7384-4

  • AD7386

  • AD7387

  • AD7388

  • AD7388-4

  • AD7389-4

  • AD4680

  • AD4681

  • AD4682

  • AD4683

  • AD4684

  • AD4685

• UG-1304, Evaluation Board User Guide

HDL related

• AD738x_FMC HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C-MIXER	library/util_i2c_mixer	—

• SPI Engine Framework documentation

Software related

• AD738X_FMC No-OS project

• AD738X_FMC - No-OS Driver [Wiki]

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.