ADRV9026 HDL reference design

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.

Supported boards

Supported devices

Supported carriers

Evaluation board

Carrier

FMC slot

ADRV9026/ADRV9029

A10SoC

FMCA

VCU118

FMCP

ZCU102

FMC HPC1

Block design

Block diagram

The data path and clock domains are depicted in the below diagrams:

Example block design for JESD204C and RX OBS in Non-LinkSharing mode

ADRV9026 JESD204C block diagram

Caution

For ZCU102 with JESD204C: REF_CLK –> 491.52 MHz (link_clk is connected to out_clk_div2 outputs of the util_adxcvr).

Block name

IP name

Documentation

Additional info

AXI_ADXCVR

axi_adxcvr

AXI ADXCVR

3 instances, one for Rx, one for Rx-os and one for Tx

AXI_CLKGEN

axi_clkgen

AXI CLK Generator

3 instances, one for Rx, one for Rx-os and one for Tx

AXI_DMAC

axi_dmac

AXI DMAC

3 instances, one for Rx, one for Rx-os and one for Tx

DATA_OFFLOAD

data_offload

Data Offload

1 instance for Tx

RX JESD LINK

axi_adrv9026_rx_jesd

JESD204B/C Link Receive Peripheral

Instantiaded by adi_axi_jesd204_rx_create procedure

RX JESD TPL

rx_adrv9026_tpl_core

ADC JESD204B/C Transport Peripheral

Instantiated by adi_tpl_jesd204_rx_create procedure

RX OS JESD LINK

axi_adrv9026_rx_os_jesd

JESD204B/C Link Receive Peripheral

Instantiaded by adi_axi_jesd204_rx_create procedure

RX OS JESD TPL

rx_os_adrv9026_tpl_core

ADC JESD204B/C Transport Peripheral

Instantiated by adi_tpl_jesd204_rx_create procedure

TX JESD LINK

axi_adrv9026_tx_jesd

JESD204B/C Link Transmit Peripheral

Instantiaded by adi_axi_jesd204_tx_create procedure

TX JESD TPL

tx_adrv9026_tpl_core

DAC JESD204B/C Transport Peripheral

Instantiated by adi_tpl_jesd204_tx_create procedure

UTIL_CPACK

util_cpack2

Channel CPACK Utility

2 instances one for Rx and one for Rx-os

UTIL_UPACK

util_upack2

Channel UPACK Utility

—

The Rx links (ADC Path) operate with the following parameters:

  • Rx Framer parameters: L=2, M=8, F=8, S=1, NP=16, E=1, K=32

  • Sample Rate: 245.76 MSPS

  • Dual link: No

  • RX_DEVICE_CLK: 245.76 MHz (Lane Rate/66)

  • REF_CLK: 245.76 MHz (Lane Rate/66)

  • JESD204C Lane Rate: 16.22 Gbps

  • QPLL0

The ORx links (ADC Obs Path) operate with the following parameters:

  • Rx Obs Framer parameters: L=2, M=4, F=4, S=1, NP=16, E=1, K=64

  • Sample Rate: 491.52 MSPS

  • Dual link: No

  • RX_OS_DEVICE_CLK: 245.76 MHz (Lane Rate/66)

  • REF_CLK: 245.76 MHz (Lane Rate/66)

  • JESD204C Lane Rate: 16.22 Gbps

  • QPLL0

The Tx links (DAC Path) operate with the following parameters:

  • Tx Deramer parameters: L=4, M=8, F=4, S=1, NP=16, E=1, K=64

  • Sample Rate: 491.52 MSPS

  • Dual link: No

  • TX_DEVICE_CLK: 245.76 MHz (Lane Rate/66)

  • REF_CLK: 245.76 MHz (Lane Rate/66)

  • JESD204C Lane Rate: 16.22 Gbps

  • QPLL0

Caution

ONLY for the ZCU102 design:

  • Cache coherency is available and enabled.

  • The DMA is connected to the Memory via HPC interface which is limited to 128 bits.

  • SYS_DMA_CLK = 333 MHz

Configuration modes

The block design supports configuration of parameters and scales.

We have listed a couple of examples at section Building the HDL project and the default modes for each project.

Note

The parameters for Rx or Tx links can be changed from the system_project.tcl file, located in hdl/projects/adrv9026/$CARRIER/system_project.tcl

\[Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{10}{8}\]

The following are the parameters of this project that can be configured:

  • JESD_MODE: used link layer encoder mode

    • 64B66B - 64b66b link layer defined in JESD204C

    • 8B10B - 8b10b link layer defined in JESD204B

  • ORX_ENABLE: Additional data path for RX-OS

    • 0 - Disabled (used for profiles with RX-OS disabled)

    • 1 - Enabled (used for profiles with RX-OS enabled)

  • TX_LANE_RATE: Transceiver line rate of the TX link

  • RX_LANE_RATE: Transceiver line rate of the RX link

  • [RX/TX/RX_OS]_JESD_M: number of converters per link

  • [RX/TX/RX_OS]_JESD_L: number of lanes per link

  • [RX/TX/RX_OS]_JESD_S: number of samples per frame

  • [RX/TX/RX_OS]_JESD_NP: number of bits per sample

  • [RX/TX/RX_OS]_TPL_WIDTH : TPL data path width in bits

  • [RX/TX/RX_OS]_NUM_LINKS: number of links

XCVR build parameters

The following parameters configure the transceiver (XCVR) link on Xilinx carriers with XCVR automation flow:

  • PLL_TYPE: the PLL used for driving the XCVR link [CPLL/QPLL0/QPLL1]

  • REF_CLK: value of the reference clock [MHz] (LANE_RATE/20 or LANE_RATE/40 for JESD204B; LANE_RATE/33 or LANE_RATE/66 for JESD204C)

  • LANE_RATE: value of the lane rate [Gbps]

Optional XCVR overrides

The following optional parameters allow configuring the RX transceiver independently from the TX path. If omitted, the RX path inherits the corresponding base parameter (PLL_TYPE, LANE_RATE, REF_CLK).

  • XCVR_RX_PLL_TYPE: RX PLL type [CPLL/QPLL0/QPLL1]

  • XCVR_RX_LANE_RATE: RX lane rate [Gbps]

  • XCVR_RX_REF_CLK: RX reference clock [MHz] (XCVR_RX_LANE_RATE/20 or XCVR_RX_LANE_RATE/40 for JESD204B; XCVR_RX_LANE_RATE/33 or XCVR_RX_LANE_RATE/66 for JESD204C)

Clock scheme

ADRV9026 ZCU102 clock scheme

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

Zynq/Microblaze

ZynqMP

rx_adrv9026_tpl_core

0x44A0_0000

0x84A0_0000

tx_adrv9026_tpl_core

0x44A0_4000

0x84A0_4000

rx_os_adrv9026_tpl_core

0x44A0_8000

0x84A0_8000

axi_adrv9026_rx_xcvr

0x44A6_0000

0x84A6_0000

axi_adrv9026_tx_xcvr

0x44A8_0000

0x84A8_0000

axi_adrv9026_rx_os_xcvr

0x45A6_0000

0x85A6_0000

axi_adrv9026_tx_jesd

0x44A9_0000

0x84A9_0000

axi_adrv9026_rx_jesd

0x44AA_0000

0x84AA_0000

axi_adrv9026_rx_os_jesd

0x45AA_0000

0x85AA_0000

axi_adrv9026_rx_dma

0x7C40_0000

0x9C40_0000

axi_adrv9026_tx_dma

0x7C42_0000

0x9C42_0000

axi_adrv9026_rx_os_dma

0x7C80_0000

0x9C80_0000

axi_adrv9026_tx_clkgen

0x43C0_0000

0x83C0_0000

axi_adrv9026_rx_clkgen

0x43C1_0000

0x83C1_0000

axi_adrv9026_rx_os_clkgen

0x43C2_0000

0x83C2_0000

adrv9026_data_offload

0x7C43_0000

0x9C43_0000

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PS

spi0

ADRV9026

0

AD9528

1

GPIOs

ZCU102

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq MP

ad9528_reset_b

INOUT

68

146

ad9528_sysref_req

INOUT

67

145

adrv9026_tx1_enable

INOUT

66

144

adrv9026_tx2_enable

INOUT

65

143

adrv9026_tx3_enable

INOUT

64

142

adrv9026_tx4_enable

INOUT

63

141

adrv9026_rx1_enable

INOUT

62

140

adrv9026_rx2_enable

INOUT

61

139

adrv9026_rx3_enable

INOUT

60

138

adrv9026_rx4_enable

INOUT

59

137

adrv9026_test

INOUT

58

136

adrv9026_reset_b

INOUT

57

135

adrv9026_gpint1

INOUT

56

134

adrv9026_gpint2

INOUT

55

133

adrv9026_orx_ctrl_a

INOUT

54

132

adrv9026_orx_ctrl_b

INOUT

53

131

adrv9026_orx_ctrl_c

INOUT

52

130

adrv9026_orx_ctrl_d

INOUT

51

129

adrv9026_gpio[0:18]

INOUT

50:32

128:110

VCU118

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Microblaze

ad9528_reset_b

INOUT

62

62

ad9528_reset_b

INOUT

61

61

adrv9026_tx1_enable

INOUT

60

60

adrv9026_tx2_enable

INOUT

59

59

adrv9026_tx3_enable

INOUT

58

58

adrv9026_tx4_enable

INOUT

57

57

adrv9026_rx1_enable

INOUT

56

56

adrv9026_rx2_enable

INOUT

55

55

adrv9026_rx3_enable

INOUT

54

54

adrv9026_rx4_enable

INOUT

53

53

adrv9026_test

INOUT

52

52

adrv9026_reset_b

INOUT

51

51

adrv9026_gpint1

INOUT

50

50

adrv9026_gpint2

INOUT

49

49

adrv9026_orx_ctrl_a

INOUT

48

48

adrv9026_orx_ctrl_b

INOUT

47

47

adrv9026_orx_ctrl_c

INOUT

46

46

adrv9026_orx_ctrl_d

INOUT

45

45

adrv9026_gpio[0:18]

INOUT

44:26

44:26

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux ZynqMP

Actual ZynqMP

axi_adrv9026_tx_jesd

10

106

138

axi_adrv9026_rx_jesd

11

107

139

axi_adrv9026_rx_os_jesd

12

108

140

axi_adrv9026_tx_dma

13

109

141

axi_adrv9026_rx_dma

14

110

142

axi_adrv9026_rx_os_dma

15

111

143

Microblaze

Instance name

HDL

Microblaze

axi_adrv9026_tx_jesd

7

7

axi_adrv9026_rx_jesd

8

8

axi_adrv9026_rx_os_jesd

15

15

axi_adrv9026_tx_dma

12

12

axi_adrv9026_rx_dma

13

13

axi_adrv9026_rx_os_dma

14

14

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the project location, choose your carrier and run the make command by typing in your command prompt. Building without parameters will use the default configuration (see the table below for default values per carrier, including XCVR parameters such as PLL_TYPE, REF_CLK and LANE_RATE).

Linux/Cygwin/WSL

~$

cd hdl/projects/adrv9026/zcu102

~/hdl/projects/adrv9026/zcu102$

make

Example for building the project with JESD parameters (XCVR parameters will use their default values):

~$

cd hdl/projects/adrv9026/zcu102

~/hdl/projects/adrv9026/zcu102$

make JESD_MODE=8B10B ORX_ENABLE=1 \
     RX_OS_JESD_M=4 RX_OS_JESD_L=2 \
     RX_OS_JESD_S=1 RX_OS_JESD_NP=16 \
     RX_JESD_L=2 RX_TPL_WIDTH=8

Example for building the project with JESD and XCVR parameters:

~$

cd hdl/projects/adrv9026/zcu102

~/hdl/projects/adrv9026/zcu102$

make JESD_MODE=8B10B ORX_ENABLE=1 \
     RX_OS_JESD_M=4 RX_OS_JESD_L=2 \
     RX_OS_JESD_S=1 RX_OS_JESD_NP=16 \
     RX_JESD_L=2 RX_TPL_WIDTH=8 \
     PLL_TYPE=QPLL0 REF_CLK=245.75 LANE_RATE=9.83 \
     XCVR_RX_PLL_TYPE=CPLL

The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used.

Parameter

Default value of the parameters depending on carrier

ZCU102/VCU118

A10SoC

XCVR build parameters

PLL_TYPE

QPLL0

—

REF_CLK

245.75

—

LANE_RATE

9.83

—

Optional XCVR overrides

XCVR_RX_PLL_TYPE

—

—

XCVR_RX_LANE_RATE

—

—

XCVR_RX_REF_CLK

—

—

JESD and other build parameters

JESD_MODE

8B10B

8B10B

ORX_ENABLE

0

—

RX_LANE_RATE

9.83

9.83

TX_LANE_RATE

9.83

9.83

TX_NUM_LINKS

1

1

RX_NUM_LINKS

1

1

RX_OS_NUM_LINKS

1

—

RX_JESD_M

8

8

RX_JESD_L

4

4

RX_JESD_S

1

1

RX_JESD_NP

16

—

RX_JESD_TPL_WIDTH

{}

—

TX_JESD_M

8

8

TX_JESD_L

4

4

TX_JESD_S

1

1

TX_JESD_NP

16

—

TX_JESD_TPL_WIDTH

{}

—

RX_OS_JESD_M

0

—

RX_OS_JESD_L

0

—

RX_OS_JESD_S

0

—

RX_OS_JESD_NP

0

—

RX_OS_JESD_TPL_WIDTH

{}

—

The result of the build, if parameters were used, will be in a folder named by the configuration used, with truncation of some keywords (JESD, LANE, etc. are removed) so the path will not exceed OS limits.

The XCVR automation flow creates a sub-build under hdl/projects/xcvr_wizard/$carrier/. For details on how the folder name is formed, see Build output folder structure.

Refer to the Build an HDL project user guide for a more comprehensive build guide.

Other considerations

ADC - lane mapping

Due to physical constraints, Rx lanes are reordered as described in the following table.

ADC phy Lane

FPGA Rx lane / Logical Lane

0

0

1

1

2

2

3

3

DAC - lane mapping

Due to physical constraints, Tx lanes are reordered as described in the following table.

DAC phy lane

FPGA Tx lane / Logical lane

0

0

1

1

2

2

3

3

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.