ADRV9026 HDL reference design

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.

Supported boards

• ADRV9026/ADRV9029

Supported carriers

Evaluation board	Carrier	FMC slot
ADRV9026/ADRV9029	A10SoC	FMCA
	ZCU102	FMC HPC1
	VCK190	FMCP1
	VCU118	FMCP

Block design

Block diagram

The data path and clock domains are depicted in the below diagrams:

Example block design for Single link; M=8; L=4

The Rx links (ADC Path) operate with the following parameters:

• Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16

• Sample Rate: 250 MSPS

• Dual link: No

• RX_DEVICE_CLK: 250 MHz (Lane Rate/40)

• REF_CLK: 500MHz (Lane Rate/20)

• JESD204B Lane Rate: 10Gbps

• QPLL0 or CPLL

The Tx links (DAC Path) operate with the following parameters:

• Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16

• Sample Rate: 250 MSPS

• Dual link: No

• TX_DEVICE_CLK: 250 MHz (Lane Rate/40)

• REF_CLK: 500MHz (Lane Rate/20)

• JESD204B Lane Rate: 10Gbps

• QPLL0 or CPLL

Configuration modes

The block design supports configuration of parameters and scales.

We have listed a couple of examples at section Building the HDL project and the default modes for each project.

Note

The parameters for Rx or Tx links can be changed from the system_project.tcl file, located in hdl/projects/adrv9026/$CARRIER/system_project.tcl

\[Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{10}{8}\]

The following are the parameters of this project that can be configured:

• JESD_MODE: used link layer encoder mode

  • 64B66B - 64b66b link layer defined in JESD204C

  • 8B10B - 8b10b link layer defined in JESD204B

• RX_LANE_RATE: lane rate of the Rx link

• TX_LANE_RATE: lane rate of the Tx link

• [RX/TX]_JESD_M: number of converters per link

• [RX/TX]_JESD_L: number of lanes per link

• [RX/TX]_JESD_S: number of samples per frame

• [RX/TX]_NUM_LINKS: number of links

Clock scheme

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Depends on parameter	Zynq/Microblaze	ZynqMP	Versal
rx_adrv9026_tpl_core		0x44A0_0000	0x84A0_0000	0xA4A0_0000
tx_adrv9026_tpl_core		0x44A0_4000	0x84A0_4000	0xA4A0_4000
axi_adrv9026_rx_xcvr	$ADI_PHY_SEL==1	0x44A6_0000	0x84A6_0000	0xA4A6_0000
axi_adrv9026_tx_xcvr	$ADI_PHY_SEL==1	0x44A8_0000	0x84A8_0000	0xA4A8_0000
axi_adrv9026_tx_jesd		0x44A9_0000	0x84A9_0000	0xA4A9_0000
axi_adrv9026_rx_jesd		0x44AA_0000	0x84AA_0000	0xA4AA_0000
axi_adrv9026_rx_dma		0x7C40_0000	0x9C40_0000	0xBC40_0000
axi_adrv9026_tx_dma		0x7C42_0000	0x9C42_0000	0xBC42_0000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	spi0	ADRV9026	0
		AD9528	1

GPIOs

ZCU102

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq MP
ad9528_reset_b	INOUT	68	146
ad9528_reset_b	INOUT	67	145
adrv9026_tx1_enable	INOUT	66	144
adrv9026_tx2_enable	INOUT	65	143
adrv9026_tx3_enable	INOUT	64	142
adrv9026_tx4_enable	INOUT	63	141
adrv9026_rx1_enable	INOUT	62	140
adrv9026_rx2_enable	INOUT	61	139
adrv9026_rx3_enable	INOUT	60	138
adrv9026_rx4_enable	INOUT	59	137
adrv9026_test	INOUT	58	136
adrv9026_reset_b	INOUT	57	135
adrv9026_gpint1	INOUT	56	134
adrv9026_gpint2	INOUT	55	133
adrv9026_orx_ctrl_a	INOUT	54	132
adrv9026_orx_ctrl_b	INOUT	53	131
adrv9026_orx_ctrl_c	INOUT	52	130
adrv9026_orx_ctrl_d	INOUT	51	129
adrv9026_gpio[0:18]	INOUT	50:32	128:110

VCU118

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Microblaze
ad9528_reset_b	INOUT	62	62
ad9528_reset_b	INOUT	61	61
adrv9026_tx1_enable	INOUT	60	60
adrv9026_tx2_enable	INOUT	59	59
adrv9026_tx3_enable	INOUT	58	58
adrv9026_tx4_enable	INOUT	57	57
adrv9026_rx1_enable	INOUT	56	56
adrv9026_rx2_enable	INOUT	55	55
adrv9026_rx3_enable	INOUT	54	54
adrv9026_rx4_enable	INOUT	53	53
adrv9026_test	INOUT	52	52
adrv9026_reset_b	INOUT	51	51
adrv9026_gpint1	INOUT	50	50
adrv9026_gpint2	INOUT	49	49
adrv9026_orx_ctrl_a	INOUT	48	48
adrv9026_orx_ctrl_b	INOUT	47	47
adrv9026_orx_ctrl_c	INOUT	46	46
adrv9026_orx_ctrl_d	INOUT	45	45
adrv9026_gpio[0:18]	INOUT	44:26	44:26

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux ZynqMP	Actual ZynqMP
axi_adrv9026_tx_jesd	10	106	138
axi_adrv9026_rx_jesd	11	107	139
axi_adrv9026_tx_dma	13	108	140
axi_adrv9026_rx_dma	14	109	141

Microblaze

Instance name	HDL	Microblaze
axi_adrv9026_tx_jesd	15	15
axi_adrv9026_rx_jesd	14	14
axi_adrv9026_tx_dma	13	13
axi_adrv9026_rx_dma	12	12

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the project location, choose your carrier and run the make command by typing in your command prompt:

Linux/Cygwin/WSL

~$

cd hdl/projects/adrv9026/zcu102

~/hdl/projects/adrv9026/zcu102$

make

~/hdl/projects/adrv9026/zcu102$

cd hdl/projects/adrv9026/a10soc

~/hdl/projects/adrv9026/zcu102/hdl/projects/adrv9026/a10soc$

make

The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used.

Default values of the make parameters for ADRV9026

Parameter	Default value of the parameters depending on carrier
	ZCU102/A10SoC/VCK190/VCU118
JESD_MODE	8B10B
RX_LANE_RATE	10
TX_LANE_RATE	10
RX_JESD_M	8
RX_JESD_L	4
RX_JESD_S	1
TX_JESD_M	8
TX_JESD_L	4
TX_JESD_S	1

A more comprehensive build guide can be found in the Build an HDL project user guide.

Other considerations

ADC - lane mapping

Due to physical constraints, Rx lanes are reordered as described in the following table.

ADC phy Lane	FPGA Rx lane / Logical Lane
0	0
1	1
2	2
3	3

DAC - lane mapping

Due to physical constraints, Tx lanes are reordered as described in the following table.

DAC phy lane	FPGA Tx lane / Logical lane
0	3
1	2
2	0
3	1

Resources

Systems related

• [Wiki] ADRV9026 & ADRV9029 Prototyping Platform User Guide

Here you can find the quick start guides available for these evaluation boards:

Evaluation board	Zynq UltraScale+ MP
ADRV9026/ADRV9029	ZCU102

Hardware related

• Product datasheet: ADRV9026

• UG-1578, Device User Guide

HDL related

• ADRV9026 HDL project source code

IP name	Source code link	Documentation link
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_UPACK2	library/util_pack/util_upack2	Channel UPACK Utility
UTIL_CPACK2	library/util_pack/util_cpack2	Channel UPACK Utility
UTIL_ADXCVR for AMD	library/xilinx/util_adxcvr	UTIL_ADXCVR core for AMD Xilinx devices
AXI_ADXCVR for Intel	library/intel/axi_adxcvr	Intel Devices
AXI_ADXCVR for AMD	library/xilinx/axi_adxcvr	AMD Xilinx Devices
AXI_JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
AXI_JESD204_TX	library/jesd204/axi_jesd204_tx	JESD204B/C Link Transmit Peripheral
JESD204_TPL_ADC	library/jesd204/ad_ip_jesd204_tpl_adc	ADC JESD204B/C Transport Peripheral
JESD204_TPL_DAC	library/jesd204/ad_ip_jesd204_tpl_dac	DAC JESD204B/C Transport Peripheral

• [Wiki] Generic JESD204B block designs

• JESD204 Interface Framework

Software related

• [Wiki] ADRV9026 Linux driver wiki page

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.