AD4134-FMC HDL project#

Overview#

The AD4134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC), based on the continuous time sigma-delta (CTSD) modulation scheme. This architecture inherently rejects signals around the ADC aliasing frequency band, giving the device its inherent antialiasing capability, and removesthe need for a complex external antialiasing filter.

This device has four independent converter channels in parallel, each with a CTSD modulator and a digital decimation and filtering path. It enables simultaneous sampling of four signal sources, with a maximum input bandwidth of 391.5 kHz. It supports a wide range of ODR frequencies, from 0.01 kSPS to 1496 kSPS wih less than 0.01 SPS adjustment resolution, allowing the user to granularly vary sampling speed to achieve coherent sampling.

The AD4134 supports two device configuration schemes: serial peripheral interface (SPI) and hardware pin configuration (pin control mode). The SPI control mode offers access to all the features and configuration options available on the chip.Pin control mode offers the benefit of simplifying the device configuration, enabling the device to operate autonomously after power-up operating in a standalone mode.

The HDL reference design for the EVAL-AD4134 provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board; to acquire continuous data from the 24-bit 4-channel precision alias free ADC device.

Supported boards#

Supported devices#

Supported carriers#

Block design#

The reference design uses the SPI Engine Framework to interface with the AD4134 ADC and only supports the slave mode with both DCLK and ODR generated by the FPGA. The device sends data on the 4 DIN bits.

Block diagram#

The data path and clock domains are depicted in the below diagrams:

AD4134-FMC/ZED block diagram

Jumper setup#

Jumper/Solder link

Position

Description

JP16

Mounted

MODE (Slave) and DCLKIO (Input)

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at HDL Architecture).

Instance

Address

spi_ad4134_axi_regmap

0x44A0_0000

axi_ad4134_dma

0x44A3_0000

odr_generator

0x44B0_0000

axi_ad4134_clkgen

0x44B1_0000

SPI connections#

SPI type

SPI manager instance

SPI subordinate

CS

PS

SPI 0

AD4134

0

GPIOs#

The Software GPIO number is calculated as follows:

  • Zynq-7000: if PS7 is used, then offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

ad4134_dclkio

INOUT

45

99

ad4134_dclk_mode

INOUT

44

98

ad4134_gpio[7:0]

INOUT

43:36

97:90

ad4134_pinbspi

INOUT

35

89

ad4134_mode

INOUT

34

88

ad4134_pdn

INOUT

33

87

ad4134_resetn

INOUT

32

86

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad4134_dma

13

57

89

spi_ad4134

12

56

88

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

1user@analog:~$ cd hdl/projects/ad4134_fmc/zed
2user@analog:~/hdl/projects/ad4134_fmc/zed$ make

A more comprehensive build guide can be found in the Build a HDL project user guide.

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.