AXI Stream FIFO#

The AXI Stream FIFO core is a simple FIFO (First Input First Output) with AXI streaming interfaces, supporting synchronous and asynchronous operation modes. It can be used to mitigate data rate differences or transfer an AXI stream to a different clock domain.

Features#

  • Supports Intel/Altera and AMD Xilinx devices

  • Configurable data width and depth

  • Supports asynchronous (double clocked) mode

  • Supports TLAST to indicate packet boundary

  • Supports FULL/EMPTY and ALMOST_FULL/ALMOST_EMPTY status signals

  • Supports zero-deep implementation

Files#

Name

Description

library/util_axis_fifo/util_axis_fifo.v

Verilog source for the peripheral.

Configuration Parameters#

Name

Description

Default Value

Choices/Range

DATA_WIDTH

Data width of AXI streaming interface.

64

8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096

ADDRESS_WIDTH

Width of the address, defines the depth of the FIFO.

5

From 0 to 4096.

ASYNC_CLK

Clocking mode. If set, the FIFO operates on asynchronous mode.

1

Synchronous (0), Asynchronous (1)

M_AXIS_REGISTERED

Add and additional register stage to the AXI stream master interface.

True

ALMOST_EMPTY_THRESHOLD

Defines the offset (in data beats) between the almost empty and empty assertion.

16

ALMOST_FULL_THRESHOLD

Defines the offset (in data beats) between the almost full and full assertion.

16

TLAST_EN

Enable TLAST logical port on the AXI streaming interface.

False

TKEEP_EN

Enable TKEEP logical port on the AXI streaming interface.

True

REMOVE_NULL_BEAT_EN

REMOVE_NULL_BEAT_EN Enable.

False

Interface#

Physical Port

Logical Port

Direction

Dependency

s_axis_valid TVALID

in

s_axis_ready TREADY

out

s_axis_data TDATA

in [63:0]

s_axis_tlast TLAST

in

TLAST_EN = 1
s_axis_tkeep TKEEP

in [7:0]

TKEEP_EN = 1

Physical Port

Logical Port

Direction

Dependency

m_axis_valid TVALID

out

m_axis_ready TREADY

in

m_axis_data TDATA

out [63:0]

m_axis_tlast TLAST

out

TLAST_EN = 1
m_axis_tkeep TKEEP

out [7:0]

TKEEP_EN = 1

Physical Port

Direction

Dependency

Description

m_axis_aclk

in

Master AXI stream clock signal Bus m_axis is synchronous to this clock domain.

m_axis_aresetn

in

Master AXI stream reset signal (active low) Bus m_axis is synchronous to this reset signal.

m_axis_level

out [4:0]

Indicates how much data is in the FIFO

m_axis_empty

out

If set, the FIFO is empty

m_axis_almost_empty

out

If set, the FIFO is almost empty

s_axis_aclk

in

Slave AXI stream clock signal Bus s_axis is synchronous to this clock domain.

s_axis_aresetn

in

Slave AXI stream reset signal (active low) Bus s_axis is synchronous to this reset signal.

s_axis_room

out [4:0]

Indicates how much space (in data beats) is in the FIFO

s_axis_full

out

If set, the FIFO is full

s_axis_almost_full

out

If set, the FIFO is almost full

Detailed Description#

The util_axis_fifo is a generic First Input First Output module, that can be used to control clock and data rate differences or to do data buffering on a AXI4 stream based data path. FIFO’s write interface is an AXI4 slave streaming interface, and the FIFO’s read interface is an AXI4 master streaming interface. The depth of the FIFO is defined by the equation, which is a function of the ADDRESS_WIDTH and DATA_WIDTH parameters:

FIFO depth in bytes = DATA_WIDTH/8 * 2 ^ ADDRESS_WIDTH

The FIFO has three different status indicator ports on both side, which provides information about the state of the FIFO for both the source and destination logic:

  • FULL or EMPTY - If these outputs are asserted, the FIFO is full or empty. In case of a full FIFO, all the write operations are suspended. In case of an empty FIFO, all the read operations are suspended.

  • ALMOST_EMPTY/ALMOST_FULL - It can be used to foresee a potential FULL or EMPTY state, asserting before the EMPTY/FULL before a predefined number of words. The offset between ALMOST_EMPTY and EMPTY, and between ALMOST_FULL and FULL can be set by using the parameters ALMOST_EMPTY_THRESHOLD and ALMOST_FULL_THRESHOLD.

  • S_AXIS_ROOM - Indicate how many words can be written in the FIFO at the current moment, until the FIFO becomes FULL.

  • M_AXIS_LEVEL - Indicate how many words can be read from the FIFO at the current moment, until the FIFO becomes EMPTY.

Important

In case of asynchronous mode, because of the delays introduced by the clock domain crossing logic, the ROOM and LEVEL indicators can not reflect the actual state of the FIFO in real time. Source and destination logic should take this into account when controlling the data stream into and from the FIFO. Carefully adjusting the ALMOST_EMPTY/ALMOST_FULL indicators can provide a safe operating margin.