Util MII to RMII#

The Util MII to RMII core is designed to interface the Zynq-7000/Zynq UltraScale+ MPSoC - PS Gigabit Ethernet MAC and Reduced Media Independent Interface (RMII) ADIN1300 PHY from the CN0506 Dual PHY Ethernet evaluation board.

Features#

Configurable interface for the MAC block (Media Independent Interface - MII or Gigabit Media Independent Interface - GMII).
Configurable data rate for the MAC block and PHY chip.

Files#

Name	Description
library/util_mii_to_rmii/util_mii_to_rmii.v	Verilog source for the main module made of the MII and RMII interfaces.
library/util_mii_to_rmii/mac_phy_link.v	Verilog source for the conversion between RMII PHY chip interface and MII MAC block interface.
library/util_mii_to_rmii/phy_mac_link.v	Verilog source for the conversion between MII MAC block interface and RMII PHY chip interface.

Block Diagram#

Configuration Parameters#

Name	Description	Default Value	Choices/Range
`INTF_CFG`	MAC Block Interface Selection	`0`	MII (0), GMII (1)
`RATE_10_100`	Data Rate Selection	`0`	100Mbps (0), 10Mbps (1)

Interface#

GMII

Enabled if INTF_CFG = 1.

MAC-PHY Link (GMII MAC Block to RMII PHY)

Physical Port	Logical Port	Direction
`mii_col`	`COL`	out
`mii_crs`	`CRS`	out
`mii_rxd`	`RXD`	out [3:0]
`mii_rx_clk`	`RX_CLK`	out
`mii_rx_dv`	`RX_DV`	out
`mii_rx_er`	`RX_ER`	out
`mac_txd`	`TXD`	in [3:0]
`mii_tx_clk`	`TX_CLK`	out
`mac_tx_en`	`TX_EN`	in
`mac_tx_er`	`TX_ER`	in

MII

Enabled if INTF_CFG = 0.

MAC-PHY Link (MII MAC Block to RMII PHY)

Physical Port	Logical Port	Direction
`mii_col`	`COL`	out
`mii_crs`	`CRS`	out
`mii_rxd`	`RXD`	out [3:0]
`mii_rx_clk`	`RX_CLK`	out
`mii_rx_dv`	`RX_DV`	out
`mii_rx_er`	`RX_ER`	out
`mac_txd`	`TXD`	in [3:0]
`mii_tx_clk`	`TX_CLK`	out
`mac_tx_en`	`TX_EN`	in
`mac_tx_er`	`TX_ER`	in

RMII

PHY-MAC Link (RMII PHY to MII MAC Block)

Physical Port	Logical Port	Direction
`phy_crs_dv`	`CRS_DV`	in
`phy_rxd`	`RXD`	in [1:0]
`phy_rx_er`	`RX_ER`	in
`rmii_txd`	`TXD`	out [1:0]
`rmii_tx_en`	`TX_EN`	out

reset_n

Active-Low reset for MII to RMII IP core

Physical Port	Logical Port	Direction	Dependency
`reset_n`	`RST`	in

ref_clk

Reference Clock for MII to RMII IP core

Physical Port	Logical Port	Direction	Dependency
`ref_clk`	`CLK`	in

Ports

Physical Port	Direction	Dependency	Description

Theory of Operation#

The following timing diagrams illustrate different signal protocols for MII and RMII interfaces at data rates of 100 and 10 Mbps.

Receive Transactions#

RMII (PHY) receive transaction at 100 Mbps with no errors and phy_crs_dv asserted until the final packet dibit. According to the RMII Specification Rev. 1.2, after the assertion of phy_crs_dv, several 00’s dibits can precede the preamble 01’s dibits. The preamble is composed of 28 “01” dibits and the start of frame delimiter of 3 “01” dibits and one “11” dibit followed by the frame containing 64-1522 bytes:

RMII (PHY) receive transaction at 100 Mbps with no errors and phy_crs_dv toggling at 25 MHz starting on a nibble boundary and indicates the PHY has lost the carrier but has accumulated nibbles to transfer:

At a data rate of 10 Mbps (ref_clk frequency divided by 10), mii_rxd will be sampled every \(10^{th}\) cycle.
MII receive transaction converted from RMII (PHY) receive transaction at 100 Mbps. In the MII mode mii_rx_dv and mii_rxd will be sampled on the falling edge of the 25 MHz mii_rx_clk and when mii_rx_dv is de-asserted, mii_rxd will present 0b0000 to the Ethernet MAC:

Transmit Transactions#

MII transmit transaction at 100 Mbps. In the MII mode mii_tx_en and mii_txd will be sampled on the rising edge of the 25 MHz mii_tx_clk:

In case of errors detection, mii_tx_er will be asserted and mii_txd dibits will be “01” for the rest of transmission to RMII interface.
At a data rate of 10 Mbps (ref_clk frequency divided by 10), mii_txd will be sampled every \(10^{th}\) cycle.
RMII transmit transaction converted from MII transmit transaction at 100 Mbps. In the RMII mode rmii_tx_en and rmii_txd will be sampled on the rising edge of the 50 MHz ref_clk:

Software Support#

Analog Devices recommends to use the provided software drivers.

Linux driver at drivers/net/mii.c
Analog Devices ADIN1300/ADIN1200 PHY Linux Driver