AD9656-FMC HDL project

Overview

The AD9656 is a quad 16-bit, 125 MSPS analog-to-digital converter (ADC) featuring an on-chip sample and hold circuit. It is designed to be low cost, low power and compact, making it easy to use.

AD9656 operates at a conversion rate of up to 125 MSPS, optimized for excellent dynamic performance and low power consumption, which is crucial for applications requiring a small package size. It requires a single 1.8 V power supply and supports LVPECL, CMOS, and LVDS-compatible sample rate clocks for full performance. The ADC does not need external reference or driver components for many applications. It also includes features to enhance flexibility and reduce system costs, such as a programmable output clock, data alignment and digital test pattern generation.

An on-chip phase-locked loop (PLL) allows users to provide a single ADC sampling clock. The PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. The configurable JESD204B output block supports up to 8.0 Gbps per lane. JESD204B output block supports one, two, and four lane configurations. The SPI control offers a wide range of flexible features to meet specific system requirements

Supported boards

• EVAL-AD9656

Supported devices

• AD9656

Supported carriers

Evaluation board	Carrier	FMC slot
EVAL-AD9656	ZCU102	FMC HPC0

Block design

Block diagram

The Rx links (ADC Path) operate with the following parameters:

• Rx Deframer parameters: L=4, M=4, S=1, NP=16, N=16

• Dual link: No

• RX_DEVICE_CLK: 62.5 MHz

• REF_CLK: 125MHz

• JESD204B Lane Rate: 10Gbps

• QPLL0 or CPLL

AD9656 FMC Card block diagram

Clock scheme

The AD9656 ADC’s default clock input is from an on-board 125MHz crystal oscillator, which goes through a transformer-coupled circuit to minimize jitter. The AD9656 has an internal clock divider (ratios 1-8) for higher frequency clocks.

There are two ways to configure the clock source for AD9656:

1. Default Configuration (On-board Oscillator):

   • The board uses a 125MHz crystal oscillator (Y801) through a transformer-coupled input network.

2. Using an External Clock Source:

   • Remove C302 (optional) and Jumper J304: This disables the on-board oscillator.

   • Attach the external clock source to the SMA connector labeled CLOCK+ (J302). The external clock should be a clean signal generator, typically ~2.8V p-p or 13 dBm sine wave input.

For more details, check EVAL-AD9656 schematic.

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	ZynqMP
rx_ad9656_tpl_core	0x84A0_0000
axi_ad9656_rx_xcvr	0x84A6_0000
axi_ad9656_rx_jesd	0x84AA_0000
axi_ad9656_rx_dma	0x9C40_0000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	AD9656	1
PS	SPI 0	AD9508	0
PS	SPI 0	AD9953	1

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux ZynqMP	Actual ZynqMP
axi_ad9656_rx_jesd	12	108	140
axi_ad9656_rx_dma	13	109	141

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9656_fmc/zcu102

~/hdl/projects/ad9656_fmc/zcu102$

make

Below are the parameters that are used to configure this project, on ZCU102.

• JESD_MODE 8B10B

• RX_NUM_OF_LANES 4

• RX_NUM_OF_CONVERTERS 4

• RX_SAMPLES_PER_FRAME 1

• RX_SAMPLE_WIDTH 16

• RX_SAMPLES_PER_CHANNEL 2

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Hardware related

• Product datasheets: AD9656

• [Wiki] Evaluating the AD9656 ADC converter

HDL related

• [Wiki] AD9656 HDL Reference Design

• AD9656-FMC HDL project source code

IP name	Source code link	Documentation link
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
AD_IP_JESD204_TPL_ADC	library/jesd204/ad_ip_jesd204_tpl_adc	ADC JESD204B/C Transport Peripheral
AXI_JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility
AXI_ADXCVR	library/xilinx/axi_adxcvr	AXI ADXCVR
UTIL_ADXCVR	library/xilinx/util_adxcvr	UTIL_ADXCVR core for AMD Xilinx devices

Software related

• No-OS project

• No-OS driver ad9467.c

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.