AD9783-EBZ HDL project

Overview

The AD9783 includes pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 16-bit resolution, and sample rates of up to 500 MSPS.

The device includes specific features for direct conversion transmit applications, including gain and offset compensation, interfacing seamlessly with analog quadrature modulators.

The EVAL-AD9783 board is connected to the FPGA carrier through AD-DAC-FMC-ADP interposer board.

Supported boards

• EVAL-AD9783

Supported devices

• AD9780

• AD9781

• AD9783

Supported carriers

• ZCU102 on FMC HPC0 slot

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

Clock scheme

• External clock source connected to J1 (CLOCK IN)

• For maximum performance, give a 500 MHz clock

To make the connection between the EVAL-AD9783 evaluation board and the carrier using SPI, some hardware changes must be done to the evaluation board. These are presented in detail in the Connections and hardware changes section.

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	ZynqMP
axi_ad9783	0x9420_0000
axi_ad9783_dma	0x9C42_0000

SPI connections

For the evaluation board to communicate through SPI with the carrier, some hardware changes must be done, which are explained in the system level documentation.

SPI type	SPI manager instance	SPI subordinate	CS nb
PS	SPI 0	AD9783	0

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux ZynqMP	Actual ZynqMP
axi_ad9783_dma	12	108	140

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9783_ebz/zcu102

~/hdl/projects/ad9783_ebz/zcu102$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Software considerations

The SPI communication is changed because of hardware modifications, so the connection looks like this:

Resources

Systems related

Here you can find the quick start guides available for these evaluation boards:

Evaluation board	Zynq UltraScale+ MP
AD9783-EBZ	[Wiki] ZCU102

Hardware related

• Product datasheets:

  • AD9780

  • AD9781

  • AD9783

  • EVAL-AD9783

  • AD-DAC-FMC-ADP

HDL related

• AD9783_EBZ HDL project source code

IP name	Source code link	Documentation link
AXI_AD9783	library/axi_ad9783	AXI AD9783
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_UPACK2	library/util_pack/util_upack2	Channel UPACK Utility

Software related

• Linux device tree zynqmp-zcu102-rev10-ad9783.dts

• Linux driver ad9783.c

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.