CN0561 HDL project#

Overview#

The AD4134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC), based on the continuous time sigma-delta (CTSD) modulation scheme. This architecture inherently rejects signals around the ADC aliasing frequency band, giving the device its inherent antialiasing capability, and removesthe need for a complex external antialiasing filter.

This device has four independent converter channels in parallel, each with a CTSD modulator and a digital decimation and filtering path. It enables simultaneous sampling of four signal sources, with a maximum input bandwidth of 391.5 kHz. It supports a wide range of ODR frequencies, from 0.01 kSPS to 1496 kSPS wih less than 0.01 SPS adjustment resolution, allowing the user to granularly vary sampling speed to achieve coherent sampling.

The AD4134 supports two device configuration schemes: serial peripheral interface (SPI) and hardware pin configuration (pin control mode). The SPI control mode offers access to all the features and configuration options available on the chip. Pin control mode offers the benefit of simplifying the device configuration, enabling the device to operate autonomously after power-up operating in a standalone mode.

The HDL reference design for the EVAL-CN0561 provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board; to acquire data from the ADC device, supporting continuous data capture at maximum 1.5 MSPS data rate. However, due to a hardware limitation, the Cora-Z7s variant will only support a maximum data clock of 24MHz, in contrast with 48MHz supported on the Zedboard.

Supported boards#

Supported devices#

Supported carriers#

Block design#

The reference design uses the SPI Engine Framework to interface with the AD4134 ADC and only supports the slave mode with both DCLK and ODR generated by the FPGA. The device sends data on the 4 DIN bits.

Block diagram#

The data path and clock domains are depicted in the below diagrams:

CN0561/ZED/Cora Z7-07S block diagram *

Legend

* The block design for Cora Z7-07S remains the same, the only difference is the data clock frequency of 24MHz.

Jumper setup#

Jumper/Solder link

Position

Description

P10

Mounted

MODE (Slave) and DEC0/DCLKIO (DCLK Input)

P13

1-2

Current sources and fault protection powered from board ±15V sources

P15

1-2

Current sources and fault protection powered from board ±15V sources

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at HDL Architecture).

Instance

Address

spi_cn0561_axi_regmap

0x44A0_0000

axi_cn0561_dma

0x44A3_0000

odr_generator

0x44B0_0000

axi_cn0561_clkgen

0x44B1_0000

SPI connections#

SPI type

SPI manager instance

SPI subordinate

CS

PS

SPI 0

AD4134

0

GPIOs#

The Software GPIO number is calculated as follows:

  • Zynq-7000: if PS7 is used, then offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

cn0561_gpio[7:4]

INOUT

42:39

96:93

cn0561_gpio[2:0]

INOUT

38:36

92:90

cn0561_pinbspi

INOUT

35

89

cn0561_mode

INOUT

34

88

cn0561_pdn

INOUT

33

87

cn0561_resetn

INOUT

32

86

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_cn0561_dma

13

57

89

spi_cn0561

12

56

88

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

1user@analog:~$ cd hdl/projects/cn0561/zed
2user@analog:~/hdl/projects/cn0561/zed$ make

A more comprehensive build guide can be found in the Build a HDL project user guide.

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.