ADAQ7980-SDZ HDL project

Overview

The ADAQ7980/ADAQ7988 are 16-bit analog-to-digital converter (ADC) subsystems that integrate four common signal processing and conditioning blocks into a system in package (SiP) design that supports a variety of applications. These devices contain the most critical passive components, eliminating many of the design challenges associated with traditional signal chains that use successive approximation register (SAR) ADCs. These passive components are crucial to achieving the specified device performance.

The ADAQ7980/ADAQ7988 contain a high accuracy, low power, 16-bit SAR ADC, a low power, high bandwidth, high input impedance ADC driver, a low power, stable reference buffer, and an efficient power management block. Housed within a tiny, 5 mm × 4 mm LGA package, these systems simplify the design process for data acquisition systems. The level of system integration of the ADAQ7980/ADAQ7988 solves many design challenges, while the devices still provide the flexibility of a configurable ADC driver feedback loop to allow gain and/or common-mode adjustments. A set of four device supplies provides optimal system performance; however, single-supply operation is possible with minimal impact on device operating specifications.

Using the SDI input, the SPI-compatible serial interface features the ability to daisy-chain multiple devices on a single, 3-wire bus and provides an optional busy indicator. The user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic. Specified operation of these devices is from −55°C to +125°C.

Applications:

• Automated test equipment (ATE)

• Battery powered instrumentation

• Communications

• Data acquisition

• Process control

• Medical instruments

Supported boards

• EVAL-ADAQ7980

Supported devices

• ADAQ7980

• ADAQ7988

Supported carriers

• ZedBoard on FMC slot

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq
axi_adaq7980_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
spi_adaq7980_adc_axi_regmap	0x44A0_0000
spi_trigger_gen	0x44B0_0000

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL	iic_main	axi_iic_main	0x4160_0000	—

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	axi_spi_engine	adaq7980	0

GPIOs

The Software GPIO number is calculated as follows:

• Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
adaq7980_rbuf_pf	INOUT	41	95
adaq7980_ref_pd	INOUT	40	94
adaq7980_gpio[7:0]	INOUT	39:32	93:86

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_adaq7980_dma	13	57	89
spi_adaq7980	12	56	88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

~$

cd hdl/projects/adaq7980_sdz/zed

~/hdl/projects/adaq7980_sdz/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Hardware related

• Product datasheet: ADAQ7980/ADAQ7988

• UG-1060, Evaluation Board User Guide

HDL related

• ADAQ7980_SDZ HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
AXI_SYSID	library/axi_sysid	AXI System ID
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	SPI Engine Offload Module

• SPI Engine Framework documentation

Software related

• ADAQ7980_SDZ No-OS project

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.