DAC JESD204B/C Transport Peripheral

The DAC JESD204B/C Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements the transport level handling of a JESD204B/C transmitter device. It is compatible with a wide range of Analog Devices high-speed digital-to-analog converters.

The core handles the JESD204B/C framing of the user-provided payload data. In addition, it is capable of generating standard and user-defined test-pattern data for interface verification. It also features a per-channel dual-tone DDS that can be used to dynamically generate test-tones.

The peripheral can be configured at runtime through a AXI4-Lite memory mapped register map.

Features

ADI high-speed DAC compatible JESD204B/C data framing;
Test-pattern generator for interface verification;
Per-channel dual-tone DDS (optional);
Runtime reconfigurability through memory-mapped register interface (AXI4-Lite).

Files

ad_ip_jesd204_tpl_dac.v

Block Diagram

../../../_images/ad_ip_jesd204_transport_dac.svg

Synthesis Configuration Parameters

Name	Description	Default Value	Choices/Range
`ID`	Instance identification number.	`0`
`FPGA_TECHNOLOGY`	Fpga Technology.	`0`	Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)
`FPGA_FAMILY`	Fpga Family.	`0`	Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)
`SPEED_GRADE`	Speed Grade.	`0`	Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)
`DEV_PACKAGE`	Dev Package.	`0`	Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)
`NUM_LANES`	Number of lanes supported by the peripheral. Equivalent to JESD204 `L` parameter.	`4`	1, 2, 3, 4, 6, 8, 12, 16, 24, 32
`NUM_CHANNELS`	Number of converters supported by the peripheral. - Equivalent to JESD204 `M` parameter.	`2`	1, 2, 4, 6, 8, 16, 32, 64
`SAMPLES_PER_FRAME`	Number of samples per frame. Equivalent to JESD204 `S` parameter.	`1`	1, 2, 3, 4, 6, 8, 12, 16
`CONVERTER_RESOLUTION`	Resolution of the converter. Equivalent to JESD204 `N` parameter.	`16`	8, 11, 12, 16
`BITS_PER_SAMPLE`	Number of bits per sample. Equivalent to JESD204 `NP` parameter.	`16`	8, 12, 16
`DMA_BITS_PER_SAMPLE`	DMA Bits per Sample.	`16`
`PADDING_TO_MSB_LSB_N`	Padding To Msb Lsb N.	`0`
`OCTETS_PER_BEAT`	Number of bytes per beat for each link.	`4`	4, 6, 8, 12, 16, 32, 64
`DDS_TYPE`	DDS Type. Set 1 for CORDIC or 2 for Polynomial	`1`	Polynominal (0), CORDIC (1)
`DDS_CORDIC_DW`	CORDIC DDS Data Width.	`16`	From 8 to 20.
`DDS_CORDIC_PHASE_DW`	CORDIC DDS Phase Width.	`16`	From 8 to 20.
`DDS_PHASE_DW`	DDS Phase Width.	`16`
`DATAPATH_DISABLE`	Disable instantiation of DDS core.	`0`
`IQCORRECTION_DISABLE`	Disable IQ Correction.	`1`
`EXT_SYNC`	Enable external SYNC.	`0`
`XBAR_ENABLE`	Enable user data XBAR.	`0`

Signal and Interface Pins

s_axi

Memory mapped AXI-lite bus that provides access to modules register map.

Physical Port	Logical Port	Direction
`s_axi_awaddr`	`AWADDR`	in [12:0]
`s_axi_awprot`	`AWPROT`	in [2:0]
`s_axi_awvalid`	`AWVALID`	in
`s_axi_awready`	`AWREADY`	out
`s_axi_wdata`	`WDATA`	in [31:0]
`s_axi_wstrb`	`WSTRB`	in [3:0]
`s_axi_wvalid`	`WVALID`	in
`s_axi_wready`	`WREADY`	out
`s_axi_bresp`	`BRESP`	out [1:0]
`s_axi_bvalid`	`BVALID`	out
`s_axi_bready`	`BREADY`	in
`s_axi_araddr`	`ARADDR`	in [12:0]
`s_axi_arprot`	`ARPROT`	in [2:0]
`s_axi_arvalid`	`ARVALID`	in
`s_axi_arready`	`ARREADY`	out
`s_axi_rdata`	`RDATA`	out [31:0]
`s_axi_rresp`	`RRESP`	out [1:0]
`s_axi_rvalid`	`RVALID`	out
`s_axi_rready`	`RREADY`	in

s_axi_aclk

All S_AXI signals and irq are synchronous to this clock.

Physical Port	Logical Port	Direction	Dependency
`s_axi_aclk`	`CLK`	in

s_axi_aresetn

Resets the internal state of the peripheral.

Physical Port	Logical Port	Direction	Dependency
`s_axi_aresetn`	`RST`	in

link

link_data: Framed transmit data towards link layer.

Physical Port	Logical Port	Direction
`link_ready`	`TREADY`	in
`link_valid`	`TVALID`	out
`link_data`	`TDATA`	out [127:0]

Ports

Physical Port	Direction	Dependency	Description
`link_clk`	in		Device clock for the JESD204B/C interface. Must be line clock/40 for 204B correct operation. Must be line clock/66 for correct 204C operation. Bus `link` is synchronous to this clock domain.
`enable`	out [1:0]		Request signal for each channel.
`dac_valid`	out [1:0]		Qualifier signal for each channel. Always ‘1’.
`dac_ddata`	in [127:0]		Raw application layer data, every channel concatenated.
`dac_dunf`	in		Application layer underflow.
`dac_rst`	out
`dac_sync_in`	in	`EXT_SYNC == 1`
`dac_sync_manual_req_out`	out	`EXT_SYNC == 1`
`dac_sync_manual_req_in`	in	`EXT_SYNC == 1`

Register Map

Base (common to all cores) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x0`	`0x0`	`VERSION`				Version and Scratch Registers
		`[31:0]`	`VERSION`	`RO`	`0x00000000`	Version number. Unique to all cores.
`0x1`	`0x4`	`ID`				Version and Scratch Registers
		`[31:0]`	`ID`	`RO`	`0x00000000`	Instance identifier number.
`0x2`	`0x8`	`SCRATCH`				Version and Scratch Registers
		`[31:0]`	`SCRATCH`	`RW`	`0x00000000`	Scratch register.
`0x3`	`0xc`	`CONFIG`				Version and Scratch Registers
		`[0]`	`IQCORRECTION_DISABLE`	`RO`	`0x0`	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
		`[1]`	`DCFILTER_DISABLE`	`RO`	`0x0`	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
		`[2]`	`DATAFORMAT_DISABLE`	`RO`	`0x0`	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
		`[3]`	`USERPORTS_DISABLE`	`RO`	`0x0`	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
		`[4]`	`MODE_1R1T`	`RO`	`0x0`	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
		`[5]`	`DELAY_CONTROL_DISABLE`	`RO`	`0x0`	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
		`[6]`	`DDS_DISABLE`	`RO`	`0x0`	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
		`[7]`	`CMOS_OR_LVDS_N`	`RO`	`0x0`	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
		`[8]`	`PPS_RECEIVER_ENABLE`	`RO`	`0x0`	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
		`[9]`	`SCALECORRECTION_ONLY`	`RO`	`0x0`	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
		`[12]`	`EXT_SYNC`	`RO`	`0x0`	If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
		`[13]`	`RD_RAW_DATA`	`RO`	`0x0`	If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.
`0x4`	`0x10`	`PPS_IRQ_MASK`				PPS Interrupt mask
		`[0]`	`PPS_IRQ_MASK`	`RW`	`0x1`	Mask bit for the 1PPS receiver interrupt
`0x7`	`0x1c`	`FPGA_INFO`				FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)
		`[31:24]`	`FPGA_TECHNOLOGY`	`RO`	`0x00`	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
		`[23:16]`	`FPGA_FAMILY`	`RO`	`0x00`	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		`[15:8]`	`SPEED_GRADE`	`RO`	`0x00`	Encoded value describing the FPGA’s speed-grade
		`[7:0]`	`DEV_PACKAGE`	`RO`	`0x00`	Encoded value describing the device package. The package might affect high-speed interfaces

DAC Common (axi_ad) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x10`	`0x40`	`RSTN`				DAC Interface Control & Status
		`[2]`	`CE_N`	`RW`	`0x0`	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		`[1]`	`MMCM_RSTN`	`RW`	`0x0`	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		`[0]`	`RSTN`	`RW`	`0x0`	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
`0x11`	`0x44`	`CNTRL_1`				DAC Interface Control & Status
		`[0]`	`SYNC`	`RW`	`0x0`	Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.
		`[1]`	`EXT_SYNC_ARM`	`RW`	`0x0`	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		`[2]`	`EXT_SYNC_DISARM`	`RW`	`0x0`	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		`[8]`	`MANUAL_SYNC_REQUEST`	`RW`	`0x0`	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
`0x12`	`0x48`	`CNTRL_2`				DAC Interface Control & Status
		`[16]`	`SDR_DDR_N`	`RW`	`0x0`	Interface type (1 represents SDR, 0 represents DDR)
		`[15]`	`SYMB_OP`	`RW`	`0x0`	Select data symbol format mode (0x1)
		`[14]`	`SYMB_8_16B`	`RW`	`0x0`	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		`[12:8]`	`NUM_LANES`	`RW`	`0x00`	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
		`[7]`	`PAR_TYPE`	`RW`	`0x0`	Select parity even (0x0) or odd (0x1).
		`[6]`	`PAR_ENB`	`RW`	`0x0`	Select parity (0x1) or frame (0x0) mode.
		`[5]`	`R1_MODE`	`RW`	`0x0`	Select number of RF channels 1 (0x1) or 2 (0x0).
		`[4]`	`DATA_FORMAT`	`RW`	`0x0`	Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		`[3:0]`	`RESERVED`	`NA`	`0x0`	Reserved
`0x13`	`0x4c`	`RATECNTRL`				DAC Interface Control & Status
		`[7:0]`	`RATE`	`RW`	`0x00`	The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
`0x14`	`0x50`	`FRAME`				DAC Interface Control & Status
		`[0]`	`FRAME`	`RW`	`0x0`	The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.
`0x15`	`0x54`	`STATUS1`				DAC Interface Control & Status
		`[31:0]`	`CLK_FREQ`	`RO`	`0x00000000`	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
`0x16`	`0x58`	`STATUS2`				DAC Interface Control & Status
		`[31:0]`	`CLK_RATIO`	`RO`	`0x00000000`	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
`0x17`	`0x5c`	`STATUS3`				DAC Interface Control & Status
		`[0]`	`STATUS`	`RO`	`0x0`	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
`0x18`	`0x60`	`DAC_CLKSEL`				DAC Interface Control & Status
		`[0]`	`DAC_CLKSEL`	`RW`	`0x0`	Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
`0x1a`	`0x68`	`SYNC_STATUS`				DAC Synchronization Status register
		`[0]`	`DAC_SYNC_STATUS`	`RO`	`0x0`	DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.
`0x1c`	`0x70`	`DRP_CNTRL`				DRP Control & Status
		`[28]`	`DRP_RWN`	`RW`	`0x0`	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		`[27:16]`	`DRP_ADDRESS`	`RW`	`0x000`	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		`[15:0]`	`RESERVED`	`RO`	`0x0000`	Reserved for backwards compatibility
`0x1d`	`0x74`	`DRP_STATUS`				DAC Interface Control & Status
		`[17]`	`DRP_LOCKED`	`RO`	`0x0`	If set indicates the MMCM/PLL is locked
		`[16]`	`DRP_STATUS`	`RO`	`0x0`	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		`[15:0]`	`RESERVED`	`RO`	`0x0000`	Reserved for backwards compatibility
`0x1e`	`0x78`	`DRP_WDATA`				DAC Interface Control & Status
		`[15:0]`	`DRP_WDATA`	`RW`	`0x0000`	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
`0x1f`	`0x7c`	`DRP_RDATA`				DAC Interface Control & Status
		`[15:0]`	`DRP_RDATA`	`RO`	`0x0000`	DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
`0x20`	`0x80`	`DAC_CUSTOM_RD`				DAC Read Configuration Data
		`[31:0]`	`DAC_CUSTOM_RD`	`RO`	`0x00000000`	Custom Read of the available registers.
`0x21`	`0x84`	`DAC_CUSTOM_WR`				DAC Write Configuration Data
		`[31:0]`	`DAC_CUSTOM_WR`	`RW`	`0x00000000`	Custom Write of the available registers.
`0x22`	`0x88`	`UI_STATUS`				User Interface Status
		`[4]`	`IF_BUSY`	`RO`	`0x0`	Interface busy. If set, indicates that the data interface is busy.
		`[1]`	`UI_OVF`	`RW1C`	`0x0`	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		`[0]`	`UI_UNF`	`RW1C`	`0x0`	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
`0x23`	`0x8c`	`DAC_CUSTOM_CTRL`				DAC Control Configuration Data
		`[31:0]`	`DAC_CUSTOM_CTRL`	`RW`	`0x00000000`	Custom Control of the available registers.
`0x28`	`0xa0`	`USR_CNTRL_1`				DAC User Control & Status
		`[7:0]`	`USR_CHANMAX`	`RW`	`0x00`	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
`0x2e`	`0xb8`	`DAC_GPIO_IN`				DAC GPIO inputs
		`[31:0]`	`DAC_GPIO_IN`	`RO`	`0x00000000`	This reads auxiliary GPI pins of the DAC core
`0x2f`	`0xbc`	`DAC_GPIO_OUT`				DAC GPIO outputs
		`[31:0]`	`DAC_GPIO_OUT`	`RW`	`0x00000000`	This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

JESD TPL (up_tpl_common) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x80`	`0x200`	`TPL_CNTRL`				JESD, TPL Control
		`[3:0]`	`PROFILE_SEL`	`RW`		Selects one of the available deframer/framers from the transport layer. Valid only if `PROFILE_NUM` > 1.
`0x81`	`0x204`	`TPL_STATUS`				JESD, TPL Status
		`[3:0]`	`PROFILE_NUM`	`RO`		Number of supported framer/deframer profiles.
`0x90 + 0x2*n`	`0x240 + 0x8*n`	`TPL_DESCRIPTORn_1`				JESD, TPL descriptor for profile n Where n is from 0 to 2.
		`[31:24]`	`JESD_F`	`RO`		Octets per Frame per Lane.
		`[23:16]`	`JESD_S`	`RO`		Samples per Converter per Frame.
		`[15:8]`	`JESD_L`	`RO`		Lane Count.
		`[7:0]`	`JESD_M`	`RO`		Converter Count.
`0x91 + 0x2*n`	`0x244 + 0x8*n`	`TPL_DESCRIPTORn_2`				JESD, TPL descriptor for profile n Where n is from 0 to 2.
		`[7:0]`	`JESD_N`	`RO`		Converter Resolution.
		`[15:8]`	`JESD_NP`	`RO`		Total Number of Bits per Sample.

DAC Channel (axi_ad*) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x100 + 0x16*n`	`0x400 + 0x58*n`	`CHAN_CNTRLn_1`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[21:16]`	`DDS_PHASE_DW`	`RO`	`0x00`	The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10. More info at AD Direct Digital Synthesis.
		`[15:0]`	`DDS_SCALE_1`	`RW`	`0x0000`	The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
`0x101 + 0x16*n`	`0x404 + 0x58*n`	`CHAN_CNTRLn_2`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`DDS_INIT_1`	`RW`	`0x0000`	The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		`[15:0]`	`DDS_INCR_1`	`RW`	`0x0000`	Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
`0x102 + 0x16*n`	`0x408 + 0x58*n`	`CHAN_CNTRLn_3`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[15:0]`	`DDS_SCALE_2`	`RW`	`0x0000`	The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
`0x103 + 0x16*n`	`0x40c + 0x58*n`	`CHAN_CNTRLn_4`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`DDS_INIT_2`	`RW`	`0x0000`	The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		`[15:0]`	`DDS_INCR_2`	`RW`	`0x0000`	Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
`0x104 + 0x16*n`	`0x410 + 0x58*n`	`CHAN_CNTRLn_5`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`DDS_PATT_2`	`RW`	`0x0000`	The DDS data pattern for this channel.
		`[15:0]`	`DDS_PATT_1`	`RW`	`0x0000`	The DDS data pattern for this channel.
`0x105 + 0x16*n`	`0x414 + 0x58*n`	`CHAN_CNTRLn_6`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[2]`	`IQCOR_ENB`	`RW`	`0x0`	if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		`[1]`	`DAC_LB_OWR`	`RW`	`0x0`	If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
		`[0]`	`DAC_PN_OWR`	`RW`	`0x0`	IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
`0x106 + 0x16*n`	`0x418 + 0x58*n`	`CHAN_CNTRLn_7`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[3:0]`	`DAC_DDS_SEL`	`RW`	`0x0`	Select internal data sources (available only if the DAC supports it). 0x00: internal tone (DDS) 0x01: pattern (SED) 0x02: input data (DMA) 0x03: 0x00 0x04: inverted pn7 0x05: inverted pn15 0x06: pn7 (standard O.150) 0x07: pn15 (standard O.150) 0x08: loopback data (ADC) 0x09: pnX (Device specific e.g. ad9361) 0x0A: Nibble ramp (Device specific e.g. adrv9001) 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
`0x107 + 0x16*n`	`0x41c + 0x58*n`	`CHAN_CNTRLn_8`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`IQCOR_COEFF_1`	`RW`	`0x0000`	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		`[15:0]`	`IQCOR_COEFF_2`	`RW`	`0x0000`	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
`0x108 + 0x16*n`	`0x420 + 0x58*n`	`USR_CNTRLn_3`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[25]`	`USR_DATATYPE_BE`	`RW`	`0x0`	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		`[24]`	`USR_DATATYPE_SIGNED`	`RW`	`0x0`	The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		`[23:16]`	`USR_DATATYPE_SHIFT`	`RW`	`0x00`	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		`[15:8]`	`USR_DATATYPE_TOTAL_BITS`	`RW`	`0x00`	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		`[7:0]`	`USR_DATATYPE_BITS`	`RW`	`0x00`	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
`0x109 + 0x16*n`	`0x424 + 0x58*n`	`USR_CNTRLn_4`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`USR_INTERPOLATION_M`	`RW`	`0x0000`	This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		`[15:0]`	`USR_INTERPOLATION_N`	`RW`	`0x0000`	This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
`0x10a + 0x16*n`	`0x428 + 0x58*n`	`USR_CNTRLn_5`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[0]`	`DAC_IQ_MODE`	`RW`	`0x0`	Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.
		`[1]`	`DAC_IQ_SWAP`	`RW`	`0x0`	Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
`0x10b + 0x16*n`	`0x42c + 0x58*n`	`CHAN_CNTRLn_9`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`DDS_INIT_1_EXTENDED`	`RW`	`0x0000`	The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		`[15:0]`	`DDS_INCR_1_EXTENDED`	`RW`	`0x0000`	Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
`0x10c + 0x16*n`	`0x430 + 0x58*n`	`CHAN_CNTRLn_10`				DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.
		`[31:16]`	`DDS_INIT_2_EXTENDED`	`RW`	`0x0000`	The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		`[15:0]`	`DDS_INCR_2_EXTENDED`	`RW`	`0x0000`	Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

Theory of Operation

Data paths

The data intended for the DAC can have multiple sources:

DMA source Raw data can be accepted from a external block representing the Application layer;
DDS source For each DAC channel, a dual-tone can be generated by a DDS core;
PRBS source For each DAC channel, one of the following PN sequence can be selected: PN7, PN15, inverted PN7, inverted PN15.

Interfaces and Signals

Application layer interface

The application layer connects to the framer block when the DMA source is selected. The framer module takes sample data and maps it onto the format that the JESD204 link expects for the specified framer configuration.

The data in the application layer interface dac_ddata is expected to have the following layout:

  MSB                                                               LSB
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]

Where MjSi refers to the i-th sample of the j-th converter. With m being the number of converters and n the number of samples per converter per beat.

The core asserts the enable signal for each channel that is enabled by the software. The dac_ddata data bus must contain data for each channel regardless if the channels are enabled or not.

Link layer interface

The link layer interface description can be found in the User Data Interface section of the JESD204B/C Link Transmit Peripheral IP.

Clock Monitor

The STATUS (0x054) register CLK_FREQ field allows to determine the clock rate of the device clock (link_clk) relative to the AXI interface clock (s_axi_aclk). This can be used to verify that the device clock is running at the expected rate.

The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.

External synchronization

By setting the EXT_SYNC parameter of the IP to 1, an external synchronization signal dac_sync_in can be used to trigger data movement from user application layer to the link layer, reset internal DDS cores or PRBS generators. If the EXT_SYNC parameter is set to zero, the external signal is ignored and only a software controlled reset happens inside the DDS, PRBS logic.

The external synchronization signal should be synchronous with the DAC clock. Synchronization will be done on the rising edge of the signal.

The self clearing SYNC control bit from the CNTRL_1 (0x44) register will arm the trigger logic to wait for the external sync signal. The DAC_SYNC_STATUS status bit from the SYNC_STATUS (0x68) register will show that the synchronization is armed but the synchronization signal has not yet been received.

Once the sync signal is received, the data will start to flow and the DAC_SYNC_STATUS status bit will reflect that with a deassertion.

While the synchronization mechanism is armed, the dac_valid output signal is gated until the trigger signal is received. The gating happens only during this period, meaning that dac_valid will stay high in all other cases (normal operation).

Restrictions

Reduced number of octets-per-frame (F) settings. The following values are supported by the peripheral: 1, 2, 4

Starting from this commit this restriction no longer applies

Software Support

Warning

To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B/C software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.

Supported Devices

JESD204B Digital-to-Analog Converters

AD9135: Dual, 11-Bit, high dynamic, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9136: Dual, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9144: Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9152: Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter
AD9154: Quad, 16-Bit, 2.4 GSPS, TxDAC+® Digital-to-Analog Converter
AD9161: 11-Bit, 12 GSPS, RF Digital-to-Analog Converter
AD9162: 16-Bit, 12 GSPS, RF Digital-to-Analog Converter
AD9163: 16-Bit, 12 GSPS, RF DAC and Digital Upconverter
AD9164: 16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
AD9172: Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
AD9173: Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
AD9174: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
AD9175: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
AD9176: Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
AD9177: Quad, 16-Bit, 12 GSPS RF DAC with Wideband Channelizers

JESD204B RF Transceivers

AD9371: SDR Integrated, Dual RF Transceiver with Observation Path
AD9375: SDR Integrated, Dual RF Transceiver with Observation Path and DPD
ADRV9009: SDR Integrated, Dual RF Transceiver with Observation Path
ADRV9008-1: SDR Integrated, Dual RF Receiver
ADRV9008-2: SDR Integrated, Dual RF Transmitter with Observation Path

JESD204B/C Mixed-Signal Front Ends

AD9081: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and Quad, 12-Bit, 4GSPS RFADC
AD9082: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and DUAL, 12-Bit, 6GSPS RFADC
AD9986: 4T2R Direct RF Transmitter and Observation Receiver
AD9988: 4T4R Direct RF Receiver and Transmitter

More Information

Technical Support

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