AD-GMSL2ETH-SL HDL project

Overview

The AD-GMSL2ETH-SL is an edge compute platform enabling low-latency data transfer from eight Gigabit Multimedia Serial Link™ (GMSL) interfaces on to a 10 Gb Ethernet link. The target applications include autonomous robots and vehicles where machine vision and real-time sensor fusion is critical.

The system includes two MAX96724 Quad Tunneling GMSL2/1 to CSI-2 Deserializers, enabling connectivity to eight GMSL cameras. The video data from the cameras is transferred from the MAX96724 deserializers via MIPI CSI2 interfaces to an AMD K26 System on Module which implements the logic to aggregate the video data from all the GMSL cameras into a 10 Gb Ethernet link, so that it can be sent to a central processing unit.

The IEEE 1588 Precision Time Protocol (PTP) with hardware timestamping is supported, enabling accurate synchronization with host systems and other edge devices. The AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner is used to generate the required clocks for the 10 Gb Ethernet interface and the PTP logic.

Supported devices

Supported carriers

Block diagram

The data path designed in this reference design is as follows:

  • the virtual channel inputs of one CSI-2 output port of the deserializer are captured using Xilinx’s MIPI CSI-2 Rx Subsystem IP

  • data is written into memory by using a Xilinx video-related DMA implementation Video Framebuffer Write

  • the control of the camera modules is realized through I2C using Xilinx’s AXI IIC logic

  • data is transmitted to a 10G-capable node by using Corundum NIC implementation

The data path and elements of the video network, 10G NIC, are depicted in the below diagram:

AD-GMSL2ETH-SL Evaluation Kit HDL-related block design

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

Address

mipi_csi2_rx_subsyst_0

0x84A0_0000

mipi_csi2_rx_subsyst_1

0x84A2_0000

axi_iic_mipi

0x84A4_0000

v_frmbuf_wr_0

0x84A6_0000

v_frmbuf_wr_1

0x84A8_0000

v_frmbuf_wr_2

0x84AA_0000

v_frmbuf_wr_3

0x84AC_0000

v_frmbuf_wr_4

0x84AE_0000

v_frmbuf_wr_5

0x84B0_0000

v_frmbuf_wr_6

0x84B2_0000

v_frmbuf_wr_7

0x84B4_0000

axi_pwm_gen_0

0x84B6_0000

corundum/s_axil_ctrl

0xA000_0000

corundum/s_axil_app_ctrl

0xA800_0000

I2C connections

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL

iic_main

axi_iic_mipi

0x84A4_0000

—

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PS

SPI0

ad9545_spi

0

GPIOs

The Software GPIO number is calculated as follows:

  • ZynqMP: if PS8 EMIOs are used, then offset is 78

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

ZynqMP

csirxss_rstn

OUT

0

78

ap_rstn_frmbuf_0

OUT

2

80

ap_rstn_frmbuf_1

OUT

3

81

ap_rstn_frmbuf_2

OUT

4

82

ap_rstn_frmbuf_3

OUT

5

83

ap_rstn_frmbuf_4

OUT

6

84

ap_rstn_frmbuf_5

OUT

7

85

ap_rstn_frmbuf_6

OUT

8

86

ap_rstn_frmbuf_7

OUT

9

87

iic_rstn

OUT

10

88

fan_pwm

INOUT

22

100

fan_tach

INOUT

23

101

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux ZynqMP

Actual ZynqMP

mipi0_csirxss_csi_irq

15

111

143

mipi1_csirxss_csi_irq

14

110

142

iic2intc_irpt

13

109

141

v_frmbuf_wr0/interrupt

12

108

140

v_frmbuf_wr1/interrupt

11

107

139

v_frmbuf_wr2/interrupt

10

106

138

v_frmbuf_wr3/interrupt

9

105

137

v_frmbuf_wr4/interrupt

8

104

136

v_frmbuf_wr5/interrupt

7

96

128

v_frmbuf_wr6/interrupt

6

95

127

v_frmbuf_wr7/interrupt

5

94

126

combined_corundum_irq

4

93

125

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:.

This project uses Corundum NIC and it needs to be cloned alongside this repository.

Publications

The following papers pertain to the Corundum source code:

  • J- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, Corundum: An Open-Source 100-Gbps NIC, in FCCM’20. (FCCM Paper, FCCM Presentation)

  • J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (Thesis)

Linux/Cygwin/WSL

~$

git clone https://github.com/corundum/corundum.git

~$

git checkout ed4a26e2cbc0a429c45d5cd5ddf1177f86838914

~$

cd hdl/projects/ad_gmsl2eth_sl/k26

~/hdl/projects/ad_gmsl2eth_sl/k26$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.