AXI AD9783#

The AXI AD9783 IP core can be used to interface the AD9783 device. It is a dual DAC with 16 bits resolution, interfaced through LVDS, and with sample rates up to 500 MSPS. This documentation only covers the IP core and requires that one must be familiar with the device for a complete and better understanding.

More about the generic framework interfacing DACs can be read in Generic AXI DAC.

Features#

  • AXI Memory-Mapped to Streaming control/status interface

  • PRBS monitoring

  • Internal DDS

  • BIST testing

  • Supports only Xilinx devices

Files#

Name

Description

library/axi_ad9783/axi_ad9783.v

Verilog source for the AXI AD9783.

library/common/up_dac_common.v

Verilog source for the DAC Common regmap.

library/common/up_dac_channel.v

Verilog source for the DAC Channel regmap.

Functional Description#

The axi_ad9783 cores architecture contains:

Device Interface Description#

The interface also provides a single clock tree for the entire core. This clock uses a global buffer that has the minimum skew all across the die. On Xilinx devices, this is done via the IBUFGDS, BUFGCE_DIV and BUFG primitives. The clock dac_clk_in_p is passed through these primitives in order to obtain the divided clock: through IBUFGDS, then BUFGCE_DIV to BUFG. The core and the interface run at the same clock frequency.

Internal Interface Description#

The main purpose of all (including this) ADI IP cores is to provide a common, well-defined internal interface within the FPGA. This interface consists of the following signals per channel, except for VALID which is common to all channels.

VALID#

It is always set to logic 1 and indicates a valid sample on each DATA port. Because it is in the transmit (DAC) direction, this indicates the current sample is being read by the core.

ENABLE#

The enable signal is only for software use and it is controlled by the corresponding register bit. The core simply reflects the programmed bit as an output port. In ADI reference projects, this bit is used to activate the channel that one is interested in. It is then used by the UPACK core to route the data based on total number of channels and the selected number of channels. As an example, AXI_AD9783 supports a total of 2 channels, 64 bits each. Because the SERDES factor was chosen to be 8, we have 4 samples of 16 bits each, on I channel and Q channel also, resulting in DMA with 128 bits as data width.

DATA#

The DATA is the raw analog samples, and 4096 samples generated by PRBS are sent. It follows two simple rules.

  1. The samples are always 16 bits. In the transmit direction, if the DAC data width is less than 16 bits, the most significant bits are used. This allows the same destination portable across different DAC data widths. In other words, if the source is generating a 16 bits tone, the signal appears the same across a 12 bit, 14 bit or 16 bit DAC with only the corresponding amplitude change. The source can thus be independent of the number of bits supported by DAC.

  2. The DATA is received and transmitted with most significant sample “newest” regardless of the channel width. In other words, the most significant sample is the “newest” sample. If the total channel width is 64 bits, it carries 4 samples (16 bits) per clock. If we were to name these samples as S3 (bits 63 down to 48), S2 (bits 47 down to 32), S1 (bits 31 down to 16) and S0 (bits 15 down to 0), the following is true. In the transmit direction, S0 is sent first and S3 is sent last to the DAC. The analog samples are S0, S1, S2 and S3 across time with S0 being the oldest and S3 being the newest sample.

Parallel data port interface#

The parallel port data interface consists of up to 18 differential signals, dac_clk_out_*, dac_clk_in_*, and up to 16 data lines (dac_data_out_*[15:0]). DCO is the output clock generated by the AD9783 that is used to clock out the data from the digital data engine.

The data lines transmit the multiplexed I and Q data words for the I and Q DACs, respectively. DCI provides timing information about the parallel data and signals the I/Q status of the data.

The incoming LVDS data is latched by an internally generated clock referred to as the data sampling signal (DSS). DSS is a delayed version of the main DAC clock signal.

The clock input signal provides timing information about the parallel data, as well as indicating the destination (that is, I DAC or Q DAC) of the data. The data that is processed on rising edge will be outputted on the I DAC, and the data that is on falling edge will be outputted on Q DAC (see figure below).

AXI AD9783 parallel interface

Calibration of the device#

Calibrating the device means finding the proper value for the SMP_DLY register (see datasheet) in order for the PRBS function (PN23 in this case) to work properly when generating the 4096 samples of data.

The BIST feature in the AD9783 is a simple type adder and is a user synchronizable BIST feature. When a reading is performed, it adds up all the data that was generated on the rising edges of the dac_div_clk and it writes it in the registers accessible by the user: the low part of the result is written in register 0x1B, and the high part in 0x1C. For the sum of data from falling edges, read 0x1D and 0x1E respectively.

register 0x1A <- 0x20
register 0x1A <- 0x00 # to clear the BIST registers
register 0x1A <- 0x80 # enable BIST
# 4096 samples generated by PN23 are sent
# send zeroes
register 0x1A <- 0xC0 # perform BIST read
# read registers 0x1B, 0x1C for the sum of data from rising edges
# read registers 0x1D, 0x1E for the sum of data from falling edges

In register 0x1A, write 0x20 then 0x00 to clear the BIST registers while the IP is writing zeros to the data bits. To enable BIST, write 0x80 to register 0x1A. Afterwards, 4096 samples of data are generated by PN23 PRBS and are sent to the data inputs. When all samples are sent, the IP is continuously sending zeros after the samples, while the BIST read is being performed. Sending zeroes after the samples is required in order to maintain the sums unchanged in the registers. Perform a BIST read by writing 0xC0 to register 0x1A to receive the unique sum of rising edge data in register 0x1B and register 0x1C and a unique sum of falling edge data in register 0x1D and register 0x1E. These register contents must always give the same values for the same samples each time they are sent. In order to change what data is sent, the DAC_DDS_SEL register value should be changed. To send PN23, 0x9 should be written in the register. The address for the DAC_DDS_SEL register is calculated by adding 0x418 (for the first channel) to the offset found in the devicetree, for the device.

Block Diagram#

AXI AD9783 block diagram

Configuration Parameters#

Name

Description

Default Value

Choices/Range

ID

Core ID should be unique for each IP in the system

0

FPGA_TECHNOLOGY

Encoded value describing the technology/generation of the FPGA device

0

Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)

FPGA_FAMILY

Encoded value describing the family variant of the FPGA device

0

Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)

SPEED_GRADE

Encoded value describing the FPGA’s speed-grade

0

Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)

DEV_PACKAGE

Encoded value describing the device package. The package might affect high-speed interfaces

0

Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)

DAC_DDS_TYPE

1 for CORDIC or 2 for Polynomial

2

DAC_DDS_CORDIC_DW

CORDIC DDS data width

16

DAC_DDS_CORDIC_PHASE_DW

CORDIC DDS phase width

16

DAC_DATAPATH_DISABLE

Disable DAC processing blocks. Disables DDS

0

Note

Make sure these parameters have the appropriate values set.

Interface#

Physical Port

Logical Port

Direction

Dependency

s_axi_awaddr AWADDR

in [15:0]

s_axi_awprot AWPROT

in [2:0]

s_axi_awvalid AWVALID

in

s_axi_awready AWREADY

out

s_axi_wdata WDATA

in [31:0]

s_axi_wstrb WSTRB

in [3:0]

s_axi_wvalid WVALID

in

s_axi_wready WREADY

out

s_axi_bresp BRESP

out [1:0]

s_axi_bvalid BVALID

out

s_axi_bready BREADY

in

s_axi_araddr ARADDR

in [15:0]

s_axi_arprot ARPROT

in [2:0]

s_axi_arvalid ARVALID

in

s_axi_arready ARREADY

out

s_axi_rdata RDATA

out [31:0]

s_axi_rresp RRESP

out [1:0]

s_axi_rvalid RVALID

out

s_axi_rready RREADY

in

Physical Port

Logical Port

Direction

Dependency

s_axi_aclk CLK

in

Physical Port

Logical Port

Direction

Dependency

s_axi_aresetn RST

in

Physical Port

Direction

Dependency

Description

dac_clk_in_p

in

LVDS input clock; comes from DCOP/N of the AD9783 chip

dac_clk_in_n

in

LVDS input clock; comes from DCOP/N of the AD9783 chip

dac_clk_out_p

out

LVDS output clock; goes to DCIP/N of the AD9783 chip

dac_clk_out_n

out

LVDS output clock; goes to DCIP/N of the AD9783 chip

dac_data_out_p

out [15:0]

LVDS output data lines

dac_data_out_n

out [15:0]

LVDS output data lines

dac_div_clk

out

Frequency divided clock used for clocking the DMA and the UPACK; it is 1/4 compared to the reference input clock

dac_rst

out

Core reset signal

dac_valid

out

Indicates valid data request for all channels

dac_dunf

in

Data underflow, must be connected to the DMA

dac_enable_*

out

If set, the channel is enabled (one for each channel)

dac_ddata_*

in [63:0]

Transmitted data output (one for each channel)

Register Map#

The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.

Register Map base addresses for axi_ad9783#

DWORD

BYTE

Name

Description

0x0000

0x0000

BASE

See the Base table for more details.

0x1000

0x4000

TX COMMON

See the DAC Common table for more details.

0x1000

0x4000

TX CHANNELS

See the DAC Channel table for more details.

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description

0x0 0x0 VERSION

Version and Scratch Registers

[31:0] VERSION RO 0x00000000

Version number. Unique to all cores.

0x1 0x4 ID

Version and Scratch Registers

[31:0] ID RO 0x00000000

Instance identifier number.

0x2 0x8 SCRATCH

Version and Scratch Registers

[31:0] SCRATCH RW 0x00000000

Scratch register.

0x3 0xc CONFIG

Version and Scratch Registers

[0:0] IQCORRECTION_DISABLE RO 0x0

If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

[1:1] DCFILTER_DISABLE RO 0x0

If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

[2:2] DATAFORMAT_DISABLE RO 0x0

If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

[3:3] USERPORTS_DISABLE RO 0x0

If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

[4:4] MODE_1R1T RO 0x0

If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

[5:5] DELAY_CONTROL_DISABLE RO 0x0

If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

[6:6] DDS_DISABLE RO 0x0

If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

[7:7] CMOS_OR_LVDS_N RO 0x0

CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

[8:8] PPS_RECEIVER_ENABLE RO 0x0

If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

[9:9] SCALECORRECTION_ONLY RO 0x0

If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)

[12:12] EXT_SYNC RO 0x0

If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

[13:13] RD_RAW_DATA RO 0x0

If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.

0x4 0x10 PPS_IRQ_MASK

PPS Interrupt mask

[0:0] PPS_IRQ_MASK RW 0x1

Mask bit for the 1PPS receiver interrupt

0x7 0x1c FPGA_INFO

FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

[31:24] FPGA_TECHNOLOGY RO 0x00

Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

[23:16] FPGA_FAMILY RO 0x00

Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

[15:8] SPEED_GRADE RO 0x00

Encoded value describing the FPGA’s speed-grade

[7:0] DEV_PACKAGE RO 0x00

Encoded value describing the device package. The package might affect high-speed interfaces

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description

0x10 0x40 RSTN

DAC Interface Control & Status

[2:2] CE_N RW 0x0

Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

[1:1] MMCM_RSTN RW 0x0

MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

[0:0] RSTN RW 0x0

Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

0x11 0x44 CNTRL_1

DAC Interface Control & Status

[0:0] SYNC RW 0x0

Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.

[1:1] EXT_SYNC_ARM RW 0x0

Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

[2:2] EXT_SYNC_DISARM RW 0x0

Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

[8:8] MANUAL_SYNC_REQUEST RW 0x0

Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

0x12 0x48 CNTRL_2

DAC Interface Control & Status

[16:16] SDR_DDR_N RW 0x0

Interface type (1 represents SDR, 0 represents DDR)

[15:15] SYMB_OP RW 0x0

Select data symbol format mode (0x1)

[14:14] SYMB_8_16B RW 0x0

Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

[12:8] NUM_LANES RW 0x00

Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)

[7:7] PAR_TYPE RW 0x0

Select parity even (0x0) or odd (0x1).

[6:6] PAR_ENB RW 0x0

Select parity (0x1) or frame (0x0) mode.

[5:5] R1_MODE RW 0x0

Select number of RF channels 1 (0x1) or 2 (0x0).

[4:4] DATA_FORMAT RW 0x0

Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

[3:0] RESERVED NA 0x0

Reserved

0x13 0x4c RATECNTRL

DAC Interface Control & Status

[7:0] RATE RW 0x00

The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.

0x14 0x50 FRAME

DAC Interface Control & Status

[0:0] FRAME RW 0x0

The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.

0x15 0x54 STATUS1

DAC Interface Control & Status

[31:0] CLK_FREQ RO 0x00000000

Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

0x16 0x58 STATUS2

DAC Interface Control & Status

[31:0] CLK_RATIO RO 0x00000000

Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

0x17 0x5c STATUS3

DAC Interface Control & Status

[0:0] STATUS RO 0x0

Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

0x18 0x60 DAC_CLKSEL

DAC Interface Control & Status

[0:0] DAC_CLKSEL RW 0x0

Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL

0x1a 0x68 SYNC_STATUS

DAC Synchronization Status register

[0:0] DAC_SYNC_STATUS RO 0x0

DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.

0x1c 0x70 DRP_CNTRL

DRP Control & Status

[28:28] DRP_RWN RW 0x0

DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

[27:16] DRP_ADDRESS RW 0x000

DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

[15:0] RESERVED RO 0x0000

Reserved for backwards compatibility

0x1d 0x74 DRP_STATUS

DAC Interface Control & Status

[17:17] DRP_LOCKED RO 0x0

If set indicates the MMCM/PLL is locked

[16:16] DRP_STATUS RO 0x0

If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

[15:0] RESERVED RO 0x0000

Reserved for backwards compatibility

0x1e 0x78 DRP_WDATA

DAC Interface Control & Status

[15:0] DRP_WDATA RW 0x0000

DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

0x1f 0x7c DRP_RDATA

DAC Interface Control & Status

[15:0] DRP_RDATA RO 0x0000

DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

0x20 0x80 DAC_CUSTOM_RD

DAC Read Configuration Data

[31:0] DAC_CUSTOM_RD RO 0x00000000

Custom Read of the available registers.

0x21 0x84 DAC_CUSTOM_WR

DAC Write Configuration Data

[31:0] DAC_CUSTOM_WR RW 0x00000000

Custom Write of the available registers.

0x22 0x88 UI_STATUS

User Interface Status

[4:4] IF_BUSY RO 0x0

Interface busy. If set, indicates that the data interface is busy.

[1:1] UI_OVF RW1C 0x0

User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

[0:0] UI_UNF RW1C 0x0

User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

0x23 0x8c DAC_CUSTOM_CTRL

DAC Control Configuration Data

[31:0] DAC_CUSTOM_CTRL RW 0x00000000

Custom Control of the available registers.

0x28 0xa0 USR_CNTRL_1

DAC User Control & Status

[7:0] USR_CHANMAX RW 0x00

This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

0x2e 0xb8 DAC_GPIO_IN

DAC GPIO inputs

[31:0] DAC_GPIO_IN RO 0x00000000

This reads auxiliary GPI pins of the DAC core

0x2f 0xbc DAC_GPIO_OUT

DAC GPIO outputs

[31:0] DAC_GPIO_OUT RW 0x00000000

This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description

0x100 + 0x16*n 0x400 + 0x58*n CHAN_CNTRLn_1

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[21:16] DDS_PHASE_DW RO 0x00

The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10. More info at AD Direct Digital Synthesis.

[15:0] DDS_SCALE_1 RW 0x0000

The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

0x101 + 0x16*n 0x404 + 0x58*n CHAN_CNTRLn_2

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_1 RW 0x0000

The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_1 RW 0x0000

Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

0x102 + 0x16*n 0x408 + 0x58*n CHAN_CNTRLn_3

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[15:0] DDS_SCALE_2 RW 0x0000

The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

0x103 + 0x16*n 0x40c + 0x58*n CHAN_CNTRLn_4

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_2 RW 0x0000

The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_2 RW 0x0000

Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

0x104 + 0x16*n 0x410 + 0x58*n CHAN_CNTRLn_5

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_PATT_2 RW 0x0000

The DDS data pattern for this channel.

[15:0] DDS_PATT_1 RW 0x0000

The DDS data pattern for this channel.

0x105 + 0x16*n 0x414 + 0x58*n CHAN_CNTRLn_6

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[2:2] IQCOR_ENB RW 0x0

if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

[1:1] DAC_LB_OWR RW 0x0

If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

[0:0] DAC_PN_OWR RW 0x0

IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

0x106 + 0x16*n 0x418 + 0x58*n CHAN_CNTRLn_7

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[3:0] DAC_DDS_SEL RW 0x0

Select internal data sources (available only if the DAC supports it). \ - 0x00: internal tone (DDS) \ - 0x01: pattern (SED) \ - 0x02: input data (DMA) \ - 0x03: 0x00 \ - 0x04: inverted pn7 \ - 0x05: inverted pn15 \ - 0x06: pn7 (standard O.150) \ - 0x07: pn15 (standard O.150) \ - 0x08: loopback data (ADC) \ - 0x09: pnX (Device specific e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

0x107 + 0x16*n 0x41c + 0x58*n CHAN_CNTRLn_8

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] IQCOR_COEFF_1 RW 0x0000

IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

[15:0] IQCOR_COEFF_2 RW 0x0000

IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

0x108 + 0x16*n 0x420 + 0x58*n USR_CNTRLn_3

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[25:25] USR_DATATYPE_BE RW 0x0

The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[24:24] USR_DATATYPE_SIGNED RW 0x0

The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[23:16] USR_DATATYPE_SHIFT RW 0x00

The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[15:8] USR_DATATYPE_TOTAL_BITS RW 0x00

The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[7:0] USR_DATATYPE_BITS RW 0x00

The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

0x109 + 0x16*n 0x424 + 0x58*n USR_CNTRLn_4

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] USR_INTERPOLATION_M RW 0x0000

This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[15:0] USR_INTERPOLATION_N RW 0x0000

This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

0x10a + 0x16*n 0x428 + 0x58*n USR_CNTRLn_5

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[0:0] DAC_IQ_MODE RW 0x0

Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.

[1:1] DAC_IQ_SWAP RW 0x0

Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.

0x10b + 0x16*n 0x42c + 0x58*n CHAN_CNTRLn_9

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_1_EXTENDED RW 0x0000

The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_1_EXTENDED RW 0x0000

Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

0x10c + 0x16*n 0x430 + 0x58*n CHAN_CNTRLn_10

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_2_EXTENDED RW 0x0000

The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_2_EXTENDED RW 0x0000

Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

Software Guidelines#

The software for this IP can be found as part of the ZCU102 Reference Design at ADI Linux repository. The IP expects the software run a calibration at least once. It has to find out what value for the SMP_DLY (see in datasheet) is good for the PRBS to work.

References#