AD4110-SDZ HDL project#

Overview#

The AD4110-1 is a complete, single-channel, universal input analog-to-digital front end for industrial process control systems where sensor type flexibility is required.

The high voltage input is fully software configurable for current or voltage ranges and allow direct interface to all standard industrial analog signal sources such as, ±20 mA, ±4 mA to ±20 mA, ±10 V, and all thermocouple types. Field power can be supplied for loop powered current output sensors. A range of excitation current sources for RTD sensors and other resistive sensors are included. The integrated programmable gain amplifier, PGA, offers sixteen gain settings from 0.2 to 24.

The high voltage input can be programmed to power up in either voltage or current mode. When programmed to current mode, the unique input circuit architecture provides a path for the loop current even in the absence of the system module power supply.

The AD4110-1 provides internal front-end diagnostic functions to indicate overvoltage, undervoltage, open wire, overcurrent and overtemperature conditions. The high voltage input is overcurrent limited and overvoltage protected up to ±35 V.

The AD4110-1 incorporates a 24-bit sigma delta analog to digital converter offering conversion rates from 5 SPS to 125 kSPS with simultaneous 50 Hz and 60 Hz noise rejection.

Applications:

  • Process control and industrial automation

  • Remote and distributed control systems

  • Instrumentation and measurement

  • Sensor and data acquisition

Supported boards#

Supported devices#

Supported carriers#

Block design#

Block diagram#

The data path and clock domains are depicted in the below diagram:

AD4110_SDZ block diagram

Jumper setup#

Jumper/Solder link

Default Position

Description

SL1

A

Connects the 5 V output of the ADP7102 to the DVDD rail to supply the IOVDD pins of the AD4110-1

SL2

A

Valid SDP connection to evaluation board LED

SL3

A

Connects J8 AINCOM to Pin 26 (AINCOM(LV)) of the AD4110-1

SL4

A

Connects GND to Pin 28 (AIN2(LV)) of the AD4110-1

SL5

A

Connects VOUT of the TMP36 temperature sensor to Pin 27 (AIN1(LV)) of the AD4110-1

Hardware setup#

Signal

AD4110 Testpoint

ZedBoard PMOD

CS

CS

JA1

DIN(MOSI)

DIN

JA2

DOUT/RDY

DOUT

JA3

SCLK

SCLK

JA10

pmod_gpio[0]

DOUT

JB1

3V3

SDP+3.3V(C43+)

JA6

GND

GND(C43-)

JA5

The evaluation board is powered by the 3.3V voltage from the ZedBoard’s PMOD (Green color of LED1 indicates valid SDP connection to the evaluation board). Also, the evaluation board is powered by a ±15V power supply connected to J14 (LED3 indicates a 5V supply to the evaluation board).

GPIOs#

The Software GPIO number is calculated as follows:

  • Zynq-7000: if PS7 is used, then the offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

pmod_gpio[3:0]

INOUT

35:32

89:86

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

1user@analog:~$ cd hdl/projects/ad4110/zed
2user@analog:~/hdl/projects/ad4110/zed$ make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.