AD469X-EVB HDL project#

Overview#

The AD469X HDL reference design provides all the interfaces that are necessary to interact with the devices on the EVAL-AD4696 board.

The design has a SPI Engine instance to control and acquire data from the AD4696 16-bit precisions ADC, providing support to capture continuous samples at maximum sampling rate. Currently the design supports the Zedboard.

Supported boards#

Supported devices#

Supported carriers#

Block design#

The reference design uses the standard SPI Engine Framework to interface the AD4696 ADC in single SDO Mode. The SPI Engine Offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device.

CNV signal gating#

The AXI PWM GEN IP core is used to drive CNV when the SPI Engine is operating in Offload mode along with logic gates and a few extra signals to ensure proper control of the signal.

The AND gate has the DMA s_axis_xfer_req signal and the PWM signal as inputs. Since the PWM is free running, this gate is necessary to prevent the sequencer on the ADC from getting out of sync. When the DMA is unable to receive more data, the s_axis_xfer_req signal is driven low, blocking the PWM signal.

Also, to exit conversion mode on the device, one extra pulse on the CNV pin is needed before sending the exit command, otherwise this command is ignored by the ADC. This feature also allows the system to read single samples using the SPI Engine FIFO mode. To achieve this, an OR gate is used to allow the software to generate CNV pulses using a GPIO signal.

Block diagram#

The data path and clock domains are depicted in the below diagram:

Zedboard#

AD469X_EVB/Zedboard block diagram

Cora Z7S#

AD469X_EVB/Cora block diagram

DE10-Nano#

AD469X_EVB/DE10-Nano block diagram

Configuration modes#

The SPI_4WIRE configuration parameter defines if CNV signal is linked to PWM or to SPI_CS to enable interfacing with a single 4-wire SPI port.

By default, it is set to 0.

Depending on the required pin functionality, some hardware modifications need to be done on the board and/or make command:

In case we link CNV signal to PWM:

make SPI_4WIRE=0

In case we link CNV signal to SPI_CS:

make SPI_4WIRE=1

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at HDL Architecture).

Instance

Zynq*/DE10-Nano**

axi_ad469x_dma*

0x44A3_0000

spi_clkgen*

0x44A7_0000

spi_ad469x_axi_regmap*

0x44A0_0000

ad469x_trigger_gen*

0x44B0_0000

axi_dmac_0**

0x0002_0000

axi_spi_engine_0**

0x0003_0000

ad469x_trigger_gen **

0x0004_0000

Legend

  • * instantiated only for Cora Z7S and Zed

  • ** instantiated only for DE10-Nano

I2C connections#

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL*

iic_fmc

axi_iic_fmc

0x4162_0000

—

PL**

iic_main

axi_ad469x_iic

0x44a4_0000

—

PS***

i2c1

sys_hps_i2c1

—

—

Legend

  • * instantiated only for Zed

  • ** instantiated only for Cora Z7S

  • *** instantiated only for DE10-Nano

SPI connections#

SPI type

SPI manager instance

SPI subordinate

CS

PL

axi_spi_engine

ad469x

0

GPIOs#

The Software GPIO number is calculated as follows:

  • Zynq-7000: if PS7 is used, then offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

ad469x_resetn

INOUT

32

86

gpio[33]

IN

33

87

gpio[34]

OUT

34

88

  • DE10-Nano: the offset is 32

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

DE10-Nano

ad469x_busy_alt_gp0;

INPUT

33

1

ad469x_resetn

INPUT

32

0

BSY_ALT_GP0 pin can be configured to function as a GPIO pin, the threshold detection alert indicator, the busy indicator, or the second serial data output in dual-sdo MODE

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad469x_dma

13

57

89

spi_ad469x

12

56

88

Instance name

HDL

Linux DE10-Nano

Actual DE10-Nano

axi_spi_engine_0

5

45

77

axi_dmac_0

4

44

76

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

user@analog:~$ cd hdl/projects/ad469x_evb/zed
user@analog:~/hdl/projects/ad469x_evb/zed$ make SPI_4WIRE=0

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

SPI_4WIRE=0

then the folder name will be:

SPI4WIRE0

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.