AD469X-EVB HDL project

The AD469X HDL reference design provides all the interfaces that are necessary to interact with the devices on the EVAL-AD4696 and EVAL-AD4692-ARDZ boards.

The design has a SPI Engine instance to control and acquire data from the AD4696/AD4692 16-bit precision ADCs, providing support to capture continuous samples at maximum sampling rate. The PWM_OFFLOAD parameter allows selecting the appropriate offload trigger and CNV gating scheme for each device.

Supported boards

Supported devices

Supported carriers

ZedBoard on FMC slot
Cora Z7S on Arduino shield connector
DE10-Nano on Arduino shield connector

Block design

The reference design uses the standard SPI Engine Framework to interface the AD4696 ADC in single SDO Mode. The SPI Engine Offload module, which can be used to capture continuous data stream at maximum data rate, is triggered depending on the PWM_OFFLOAD parameter (see Configuration modes).

CNV signal gating

The AXI PWM GEN IP core is used to drive CNV when the SPI Engine is operating in Offload mode along with logic gates and a few extra signals to ensure proper control of the signal.

In the default mode (PWM_OFFLOAD=0), the AND gate has the DMA s_axis_xfer_req signal and the PWM signal as inputs. Since the PWM is free running, this gate is necessary to prevent the sequencer on the ADC from getting out of sync. When the DMA is unable to receive more data, the s_axis_xfer_req signal is driven low, blocking the PWM signal.

In register mode (PWM_OFFLOAD=1), the AND gate has the PWM signal and the BUSY signal as inputs, gating the CNV based on the ADC busy state.

In both modes 0 and 1, an OR gate allows the software to generate CNV pulses using a GPIO signal. This is needed to exit conversion mode on the device, as one extra pulse on the CNV pin is required before sending the exit command. This also allows the system to read single samples using the SPI Engine FIFO mode.

In manual mode (PWM_OFFLOAD=2), no CNV gating is used. Instead, the SPI Engine offload trigger itself is gated by an AND of the PWM and DMA s_axis_xfer_req signals.

Block diagram

Default mode (PWM_OFFLOAD=0)

The data path and clock domains are depicted in the below diagrams. These diagrams correspond to the default configuration (PWM_OFFLOAD=0), where the BUSY falling edge triggers the SPI Engine offload and the CNV signal is gated by DMA s_axis_xfer_req AND PWM, with a GPIO OR override.

Zedboard

Cora Z7S

DE10-Nano

AD4692 register mode (PWM_OFFLOAD=1)

In register mode, the SPI Engine offload is triggered by the BUSY falling edge, same as the default mode. The difference is in the CNV gating: instead of gating with DMA s_axis_xfer_req, the CNV signal is gated by an AND of the PWM signal and the BUSY signal. An OR gate with a GPIO signal is still present to allow software-generated CNV pulses.

AD4692/Cora Z7S register mode block diagram

AD4692 manual mode (PWM_OFFLOAD=2)

In manual mode, the SPI Engine offload trigger is gated by an AND of the PWM signal and the DMA s_axis_xfer_req signal. This ensures that SPI transactions only occur when both the PWM fires and the DMA is ready to receive data. No CNV gating logic is instantiated.

AD4692/Cora Z7S manual mode block diagram

Configuration modes

The SPI_4WIRE configuration parameter defines if CNV signal is linked to PWM or to SPI_CS to enable interfacing with a single 4-wire SPI port.

By default, it is set to 0.

Depending on the required pin functionality, some hardware modifications need to be done on the board and/or make command:

In case we link CNV signal to PWM:

~$

make SPI_4WIRE=0 PWM_OFFLOAD=0

In case we link CNV signal to SPI_CS:

~$

make SPI_4WIRE=1 PWM_OFFLOAD=0

The PWM_OFFLOAD configuration parameter defines the SPI Engine offload trigger source and CNV gating scheme. By default, it is set to 0.

PWM_OFFLOAD=0: BUSY falling edge triggers offload, CNV gated by DMA xfer_req AND PWM (original ad469x).
PWM_OFFLOAD=1: BUSY falling edge triggers offload, CNV gated by PWM AND BUSY (ad4692 register mode).
PWM_OFFLOAD=2: PWM AND DMA xfer_req gates offload trigger, no CNV gating (ad4692 manual mode).

~$

make SPI_4WIRE=0 PWM_OFFLOAD=1

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at CPU/Memory interconnects addresses).

Instance	Zynq/DE10-Nano*
axi_ad469x_dma*	0x44A3_0000
spi_clkgen*	0x44A7_0000
spi_ad469x_axi_regmap*	0x44A0_0000
ad469x_trigger_gen*	0x44B0_0000
axi_dmac_0**	0x0002_0000
axi_spi_engine_0**	0x0003_0000
ad469x_trigger_gen **	0x0004_0000

Legend

* instantiated only for Cora Z7S and Zed
** instantiated only for DE10-Nano

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL*	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL**	iic_ard	axi_iic_ard	0x4160_0000	—
PS***	i2c1	sys_hps_i2c1	—	—

Legend

* instantiated only for Zed
** instantiated only for Cora Z7S
*** instantiated only for DE10-Nano

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	axi_spi_engine	ad469x	0

GPIOs

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
ad469x_resetn	INOUT	32	86
gpio[33]	IN	33	87
gpio[34]	OUT	34	88

DE10-Nano: the offset is 32

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		DE10-Nano
ad469x_busy_alt_gp0;	INPUT	33	1
ad469x_resetn	INPUT	32	0

BSY_ALT_GP0 pin can be configured to function as a GPIO pin, the threshold detection alert indicator, the busy indicator, or the second serial data output in dual-sdo MODE

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ad469x_dma	13	57	89
spi_ad469x	12	56	88
axi_iic_ard	11	55	87

Instance name	HDL	Linux DE10-Nano	Actual DE10-Nano
axi_spi_engine_0	5	45	77
axi_dmac_0	4	44	76

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad469x_evb/zed

~/hdl/projects/ad469x_evb/zed$

make SPI_4WIRE=0 PWM_OFFLOAD=0

or, for the AD4692 in register mode on Cora Z7S:

~$

cd hdl/projects/ad469x_evb/coraz7s

~/hdl/projects/ad469x_evb/coraz7s$

make SPI_4WIRE=0 PWM_OFFLOAD=1

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

SPI_4WIRE=0 PWM_OFFLOAD=1

then the folder name will be:

SPI4WIRE0_PWMOFFLOAD1

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

AD469X_EVB HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
AXI_SYSID	library/axi_sysid	AXI System ID
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—

SPI Engine Framework documentation

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.