AXI Clock Monitor

The AXI Clock Monitor IP is used to measure clocks in the system. It allows up to 16 clocks to be measured at a time.

Features

• Can measure up to 16 clocks (set to 1 by default)

• AXI-based configuration

• Vivado and Quartus compatible

Files

Name	Description
library/axi_clock_monitor/axi_clock_monitor.v	Verilog source for the instance
library/axi_clock_monitor/axi_clock_monitor_ip.tcl	Tcl source describing the instance for Vivado
library/axi_clock_monitor/axi_clock_monitor_hw.tcl	Tcl source describing the instance for Quartus

Configuration Parameters

Name	Description	Default Value	Choices/Range
FPGA_TECHNOLOGY	Encoded value describing the technology/generation of the FPGA device (7series,ultrascale,ultradcale+,versal).	0	Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)
ID	Core ID should be unique for each IP in the system.	0
NUM_OF_CLOCKS	Select number of CLOCKS.	1	From 1 to 16.
DIV_RATE	This parameter can take the following values: 1, 2, 4, 8.	1

Interface

s_axi

Physical Port	Logical Port	Direction	Dependency
s_axi_awaddr	AWADDR	in [15:0]
s_axi_awprot	AWPROT	in [2:0]
s_axi_awvalid	AWVALID	in
s_axi_awready	AWREADY	out
s_axi_wdata	WDATA	in [31:0]
s_axi_wstrb	WSTRB	in [3:0]
s_axi_wvalid	WVALID	in
s_axi_wready	WREADY	out
s_axi_bresp	BRESP	out [1:0]
s_axi_bvalid	BVALID	out
s_axi_bready	BREADY	in
s_axi_araddr	ARADDR	in [15:0]
s_axi_arprot	ARPROT	in [2:0]
s_axi_arvalid	ARVALID	in
s_axi_arready	ARREADY	out
s_axi_rdata	RDATA	out [31:0]
s_axi_rresp	RRESP	out [1:0]
s_axi_rvalid	RVALID	out
s_axi_rready	RREADY	in

s_axi_aclk

Physical Port	Logical Port	Direction	Dependency
s_axi_aclk	CLK	in

s_axi_aresetn

Physical Port	Logical Port	Direction	Dependency
s_axi_aresetn	RST	in

reset

Physical Port	Logical Port	Direction	Dependency
reset	RST	out

Ports

Physical Port	Direction	Dependency	Description
clock_*	in

Detailed Description

The top module instantiates:

• the clock monitor module

• the AXI handling interface

How to instantiate it in your project:

1. build this IP by going to the library/axi_clock_monitor folder and running make. For more details on building this, check out our guide. Another requirement is to have your desired project already built.

2. import the IP core to your block design, by opening the Block Design of the already built project, right-clicking in the Diagram then “Add IP” (or CTRL + I) and typing “axi_clock_monitor”

3. configure your IP by specifying how many clocks you want to monitor

4. connect the IP to the AXI interface

5. assign a base address to the IP core, such that it doesn’t overlap with other components

6. assign clock signals to the clock inputs

7. build again the HDL (now containing this module as well) by clicking “Generate Bitstream” from “Program and Debug” section in Vivado

Register Map

Clock Monitor (axi_clock_monitor) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
0x0	0x0	PCORE_VERSION				PCORE Version Registers
		[31:0]	PCORE_VERSION	RO	0x00000001	PCORE Version number
0x1	0x4	ID				ID Registers
		[31:0]	ID	RW	0x00000000	Instance identifier number
0x3	0xc	NUM_OF_CLOCKS				Number of Clocks Registers
		[31:0]	NUM_OF_CLOCKS	RW	0x00000008	Number of clock inputs
0x2	0x8	DIV_RATE				Divider Rate Registers
		[7:0]	DIV_RATE	RW	0x01	Number of divider rate
0x4	0x10	OUT_RESET				Reset Control Registers
		[0]	RESET	RW	0x0	Control the out reset signal
0x10 + 0x1*n	0x40 + 0x4*n	CLOCK_n				Measured clock_n Where n is from 0 to 15.
		[31:0]	CLOCK_n	RO	0x00000000	Measured frequency of clock_n

Software Guidelines

Note

Only no-OS software is supported.

We use software to access the core’s registers to get the data from the IP.

The following example contains a simple function that reads all the info from the IP and prints it on the serial terminal:

void clock_monitor_info (uint32_t core_base_addr, uint32_t axi_clock_speed_mhz) {
   uint32_t clock_ratio = 0;
   uint32_t clk1_addr = 0x40;
   uint32_t n_clocks = 0;
   uint32_t info_var = 0;
   uint8_t n = 0;

   info_var = axi_io_read(core_base_addr);
   printf("PCORE_VERSION = %d\n", info_var);

   info_var = axi_io_read(core_base_addr, 4);
   printf("ID = %d\n", info_var);

   n_clocks = axi_io_read((core_base_addr, 12));
   printf("n clocks = %d\n", n_clocks);

   info_var = axi_io_read(core_base_addr, 16);
   printf("RESET OUT = %d\n", info_var);

   while (n < n_clocks & n < 16) {
      clock_ratio = axi_io_read((core_base_addr, clk1_addr + 4*n));

      if (clock_ratio == 0) {
         printf("Measured clock_%d: off\n", n);
      } else {
         printf("Measured clock_%d: %d MHz\n", n,
            (clock_ratio * axi_clock_speed_mhz + 0x7fff) >> 16);
      }
      n++;
   }
}

To call the function, consider the following parameters:

• core_base_addr will take the value of the base address set at step 5 of the HDL instantiation

• axi_clock_speed_mhz will be the reference frequency. In most cases, we assume this parameter to be 100 [MHz]