DAC-FMC-EBZ HDL project#

Overview#

The DAC-FMC-EBZ HDL project is a wrapper for many DAC-based evaluation boards, all having similar interfaces, which are listed below. Each evaluation board has its particularities, which are supported in this design and can be selected by changing some parameters before building the project.

Supported boards#

Supported devices#

Supported carriers#

Evaluation board

Carrier

FMC slot
AD9135-FMC-EBZ
AD9136-FMC-EBZ
AD9144-FMC-EBZ
AD9152-FMC-EBZ
AD9154-FMC-EBZ
AD917x-FMC-EBZ

A10SoC

FMCA

VCU118

FMC+

ZC706

FMC HPC

ZCU102

FMC HPC0

AD916x-FMC-EBZ

VCU118

FMC+

ZC706

FMC HPC

ZCU102

FMC HPC0

Block design#

Block diagram#

The data path and clock domains are depicted in the below diagram:

DAC-FMC-EBZ block diagram

The data to be sent to DAC can have multiple sources:

DMA source#

In cases of high sample rates where the required data rate exceeds the PS-PL interface’s available throughput, the data is transmitted in a loop from a local buffer (dac_fifo) which is loaded once with the DMA from the PS DDR.

For lower sample rates, the DAC FIFO can be placed in bypass mode, in which case the DMA must stream the data from the PS memory.

DDS source#

For each DAC channel a tone is generated by a DDS core.

PRBS source#

For each DAC channel, one of the following PN sequences can be selected: PN7, PN15, inverted PN7, inverted PN15.

Software-defined pattern source#

For each DAC channel, software can set the values that will be driven to the DAC.

Configuration modes#

The configuration parameters that can be set along with the make command are:

  • ADI_DAC_DEVICE: specifies the DAC device

    • AD9172 (default)

    • AD9135

    • AD9136

    • AD9144

    • AD9154

    • AD9152

    • AD9161

    • AD9162

    • AD9163

    • AD9164

    • AD9171

    • AD9173

  • ADI_DAC_MODE: specifies the JESD operation mode

    • 04 (default)

    • can vary from 00 to 21 depending on the selected device (ADI_DAC_DEVICE)

  • ADI_LANE_RATE: specifies the lane rate (supported only on the ZCU102 carrier)

    • 15.4 GHz(default)

    • 12.5 GHz

If the desired parameters are not listed in any of the supported modes the user can configure them trough make parameters:

  • M: number of converters per link

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

  • L: number of lanes per link

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

  • S: number of samples per frame

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

  • F: number of octets per frame

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

  • HD: high-density

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

  • N: converter resolution

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

  • NP: number of bits per sample

    • the value set by the ADI_DAC_MODE (default)

    • according to the datasheet

Mode

JESD parameters

M

L

S

F

HD

N

NP

08

1

4

2

1

1

16

16

09

1

2

1

1

1

16

16

10

1

1

1

2

0

16

16

11

2

8

2

1

1

16

16

12

2

4

1

1

1

16

16

13

2

2

1

2

0

16

16

Mode

JESD parameters

M

L

S

F

HD

N

NP

00

4

8

1

1

1

16

16

01

4

8

2

2

0

16

16

02

4

4

1

2

0

16

16

03

4

2

1

4

0

16

16

04

2

4

1

1

1

16

16

05

2

4

2

2

0

16

16

06

2

2

1

2

0

16

16

07

2

1

1

4

0

16

16

09

1

2

1

1

1

16

16

10

1

1

1

2

0

16

16

Mode

JESD parameters

M

L

S

F

HD

N

NP

04

2

4

1

1

1

16

16

05

2

4

2

2

0

16

16

06

2

2

1

2

0

16

16

07

2

1

1

4

0

16

16

09

1

2

1

1

1

16

16

10

1

1

1

2

0

16

16

Mode

JESD parameters

M

L

S

F

HD

N

NP

01

2

1

1

4

1

16

16

02

2

2

2

2

1

16

16

03

2

3

3

4

1

16

16

04

2

4

1

1

1

16

16

06

2

6

3

2

1

16

16

08

2

8

2

1

1

16

16

09

1

8

4

1

1

16

16

Mode

JESD parameters

M

L

S

F

HD

N

NP

00

2

1

1

4

1

16

16

03

2

2

1

2

1

16

16

Mode

JESD parameters

M

L

S

F

HD

N

NP

00

2

1

1

4

1

16

16

01

4

2

1

4

1

16

16

02

6

3

1

4

1

16

16

03

2

2

1

2

1

16

16

04

4

4

1

2

1

16

16

08

2

4

1

1

1

16

16

09

2

4

2

2

1

16

16

10

2

8

2

1

1

16

16

11

2

8

4

2

1

16

16

18

1

4

2

1

1

16

16

19

1

4

4

2

1

16

16

20

1

8

4

1

1

16

16

21

1

8

8

2

1

16

16

Mode

JESD parameters

M

L

S

F

HD

N

NP

00

2

1

1

4

1

16

16

01

4

2

1

4

1

16

16

02

6

3

1

4

1

16

16

03

2

2

1

2

1

16

16

04

4

4

1

2

1

16

16

08

2

4

1

1

1

16

16

09

2

4

2

2

1

16

16

13

2

4

1

1

1

16

16

14

2

4

2

2

1

16

16

15

2

8

2

1

1

16

16

16

2

8

4

2

1

16

16

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at HDL Architecture).

Instance

Zynq/Microblaze

ZynqMP

dac_jesd204_xcvr

0x44A6_0000

0x84A6_0000

dac_jesd204_transport

0x44A0_4000

0x84A0_4000

dac_jesd204_link

0x44A9_0000

0x84A9_0000

dac_dma

0x7C42_0000

0x9C42_0000

Instance

A10SoC

dac_jesd204_transport

0x0003_0000

dac_dma

0x0004_0000

dac_jesd204_link.link_reconfig

0x0002_0000

dac_jesd204_link.link_management

0x0002_4000

dac_jesd204_link.link_pll_reconfig

0x0002_5000

dac_jesd204_link.lane_pll_reconfig

0x0002_6000

dac_jesd204_link.phy_reconfig_0*

0x0002_8000

dac_jesd204_link.phy_reconfig_1*

0x0002_9000

dac_jesd204_link.phy_reconfig_2*

0x0002_A000

dac_jesd204_link.phy_reconfig_3*

0x0002_B000

dac_jesd204_link.phy_reconfig_4*

0x0002_C000

dac_jesd204_link.phy_reconfig_5*

0x0002_D000

dac_jesd204_link.phy_reconfig_6*

0x0002_E000

dac_jesd204_link.phy_reconfig_7*

0x0002_F000

Note

  • * - one for each lane, depends on the number of lanes; if L=4, then only _0->_3 will exist.

SPI connections#

Important

spi_en is:

  • active HIGH for AD913X, AD91X4, AD915X and AD916X evaluation boards

  • active LOW for AD917X evaluation boards

SPI type

SPI manager instance

SPI subordinate

CS

ZC706/ZCU102

A10SoC/VCU118

ZC706/ZCU102

A10SoC/VCU118

PS

PL

SPI 0

SYS_SPI/AXI_SPI

HMC7044

0

PS

PL

SPI 0

SYS_SPI/AXI_SPI

AD913x/AD91x4/AD915x/AD916x/AD917x

1

PS

PL

SPI 0

SYS_SPI/AXI_SPI

ADF4355*

2

PS

—

SPI 1

—

PMOD**

0

Note

  • * - only when the selected device is AD916x.

  • ** - only on the ZC706/ZCU102 carriers

GPIOs#

GPIO signal

Direction (from FPGA view)

HDL GPIO EMIO

Software GPIO Zynq MP

Software GPIO Microblaze

Software GPIO Arria 10

Xilinx

Intel

pmod_gpio[3:0]*

INOUT

51-48

—

128-125

51-48

—

dac_fifo_bypass

OUTPUT

40

40

117

40

8

dac_ctrl[4]

INOUT

25

—

102

25

—

dac_ctrl[3]

INOUT

24

35

101

24

3

dac_ctrl[2]

INOUT

23

34

100

23

2

dac_ctrl[1]

INOUT

22

33

99

22

1

dac_ctrl[0]

INOUT

21

32

98

21

0

Note

  • * - only on the ZC706/ZCU102 carriers

GPIO signal

Function

AD91X4/AD915X/AD913X

AD916X

AD917X

dac_ctrl[4]

NC

FMC_HMC849VCTL

NC

dac_ctrl[3]

FMC_TXEN_1

NC

NC

dac_ctrl[2]

NC

NC

FMC_TXEN_1

dac_ctrl[1]

NC

NC

FMC_TXEN_0

dac_ctrl[0]

FMC_TXEN_0

FMC_TXEN_0

FMC_PE_CTRL

Note

NC - not connected

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Microblaze

Linux ZynqMP

Actual ZynqMP

A10SoC

dac_dma

12

13

108

140

—

dac_dma*

11

—

—

—

30

dac_jesd204_link

10

15

106

138

—

dac_jesd204_link*

9

—

—

—

28

Note

  • * - only on the A10SoC carrier

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the hdl/projects/dac_fmc_ebz location, choose the desired carrier and run the make command by typing in your command prompt:

The default configuration, regardless of the carrier, is ADI_DAC_DEVICE=AD9172 ADI_DAC_MODE=04.

user@analog:~$ cd hdl/projects/dac_fmc_ebz/zcu102
user@analog:~/hdl/projects/dac_fmc_ebz/zcu102$ make

Example: if the AD9164 device is needed and the mode should be 08, the following command should be run:

user@analog:~$ cd hdl/projects/dac_fmc_ebz/zcu102
user@analog:~/hdl/projects/dac_fmc_ebz/zcu102$ make ADI_DAC_DEVICE=AD9164 ADI_DAC_MODE=08

Example: if the AD9164 device is needed and there is a need for a custom mode , the following commands should be run:

make ADI_DAC_DEVICE=AD9164 ADI_LANE_RATE=12.5 M=1 L=8 S=4 F=1 HD=1 N=16 NP=16

or:

make ADI_DAC_DEVICE=AD9164  ADI_LANE_RATE=12.5 ADI_DAC_MODE= 08 M=1 S=4

With either of these two options, the design will be built in the same configuration:

ADI_DAC_DEVICE=AD9164 LANE_RATE=12.5GHz M=1 L=8 S=4 F=1 HD=1 N=16 NP=16

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run make ADI_DAC_DEVICE=AD9164 ADI_DAC_MODE=08 then the folder name will be: ADIDACDEVICEAD9164_ADIDACMODE08

A more comprehensive build guide can be found in the Build an HDL project user guide.

Software considerations#

DAC - crossbar config#

Due to physical constraints, Tx lanes are reordered as described in the following table:

DAC phy Lane

FPGA Tx lane / Logical Lane

0

0

1

1

2

2

3

3

4

7

5

4

6

6

7

5

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.