AD6676EVB HDL project

Overview

The AD6676-EBZ supports the AD6676 highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz.

Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture.

On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting lane rates up to 5.333 Gbps.

Supported boards

  • EVAL-AD6676 (also referred to as AD6676EVB/AD6676-EBZ)

Supported devices

Supported carriers

Evaluation board

Carrier

FMC slot

EVAL-AD6676

VC707

FMC1 HPC

ZC706

FMC HPC

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

AD6676EVB block diagram

Configuration modes

The only parameter of this project that can be configured is RX_JESD_L: number of lanes per link. Possible values: {1, 2}.

Clock scheme

By default, the evaluation board uses the local oscillator configured at 200 MHz.

  • For external CLKIN signal source, remove both R95 and R100 (see the eval. board schematic for more details)

  • For local oscillator CLKIN signal source, the Y1 quad frequency oscillator can be configured to use one of the frequencies: 125 MHz, 150 MHz, 200 MHz, 250 MHz (check the eval. board schematic)

Limitations

The design has one JESD receive chain with 2 lanes. The JESD204B lane rates for AD6676 are in range 3.072Gbps-5.333Gbps, depending on the output data rate (\(F_{DATA\_IQ} = \frac{F_{ADC}}{Decim.}\)) and the number of lanes used, but in this configuration, with

FADC = 3200 MHz
Decimation = 16
L = 2

we have JESD204B lane rate = 4 GSPS

\[\begin{split}Lane Rate &= \frac{M * NP * \frac{10}{8} * \frac{F_{ADC}}{Decim.}}{L} \\ &= \frac{40 * \frac{3200}{16}}{2} = 4000 MSPS\end{split}\]

The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The link operates in Subclass 1.

The link is set for full bandwidth mode and operate with the following parameters:

  • Used link layer encoder mode is 8B10B, defined in JESD204B, which uses ADI IP as Physical Layer

  • RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA): 4 Gbps

  • REF_CLK_RATE: the rate of the reference clock: 200 MHz

  • M: 2 converters per link

  • S: 1 sample per frame

  • NP: 16 bits per sample, and converter resolution: 16 (N)

  • F: 2 octets per frame in case of L=2, and 4 in case of L=1

For more details, check Table 19, JESD204B Output Configurations from the AD6676 data sheet.

Deframer paramaters: L=2, M=2, F=2, S=1, NP=16

REFCLK - 200 MHz (Lane Rate/20)
DEVICE CLK - 100 MHz (Lane Rate/40)
ADC CLK - 3200 MHz
JESD204B Lane Rate - 4 Gbps

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

Zynq/Microblaze/Virtex

axi_ad6676_core

0x44A1_0000

axi_ad6676_xcvr

0x44A6_0000

axi_ad6676_jesd

0x44AA_0000

axi_ad6676_dma

0x7C42_0000

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PS

SPI 0

AD6676

0

GPIOs

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

Software GPIO

(from FPGA view)

Zynq-7000

Zynq MP

adc_oen

INOUT

41

95

119

adc_sela

INOUT

40

94

118

adc_selb

INOUT

39

93

117

adc_s0

INOUT

38

92

116

adc_s1

INOUT

37

91

115

adc_resetb

INOUT

36

90

114

adc_agc1

INOUT

35

89

113

adc_agc2

INOUT

34

88

112

adc_agc3

INOUT

33

87

111

adc_agc4

INOUT

32

86

110

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad6676_dma

13

57

89

axi_ad6676_jesd

12

56

88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Linux/Cygwin/WSL

Building the VC707/ZC706 project with the default configuration, RX_JESD_L=2 lanes.

~$

cd hdl/projects/ad6676evb/vc707

~/hdl/projects/ad6676evb/vc707$

make

~$

cd hdl/projects/ad6676evb/zc706

~/hdl/projects/ad6676evb/zc706$

make

Building the VC707/ZC706 project with the other available configuration, with just one lane:

~$

cd hdl/projects/ad6676evb/vc707

~/hdl/projects/ad6676evb/vc707$

make RX_JESD_L=1

~$

cd hdl/projects/ad6676evb/zc706

~/hdl/projects/ad6676evb/zc706$

make RX_JESD_L=1

The result of the build, if parameters were used, will be in a folder named by the configuration used: hdl/projects/ad6676evb/$CARRIER/RXL1.

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.