CN0363 DMA Sequencer

The CN0363 Sequencer FPGA Peripheral is part of the CN0363 HDL project and is responsible to sequence the various data channels to the DMA.

Files

Name	Description
library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v	Verilog source for the peripheral.
library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl	TCL script to generate the Vivado IP-integrator project for the peripheral.

Interface

phase

AXI-Stream slave - Phase data channel.

Physical Port	Logical Port	Direction	Dependency
phase_valid	TVALID	in
phase_ready	TREADY	out
phase	TDATA	in [31:0]

data

AXI-Stream slave - Sample data channel.

Physical Port	Logical Port	Direction	Dependency
data_valid	TVALID	in
data_ready	TREADY	out
data	TDATA	in [23:0]

data_filtered

AXI-Stream slave - Filtered sample data channel.

Physical Port	Logical Port	Direction	Dependency
data_filtered_valid	TVALID	in
data_filtered_ready	TREADY	out
data_filtered	TDATA	in [31:0]

i_q

AXI-Stream slave - Demodulated I/Q sample data channel.

Physical Port	Logical Port	Direction	Dependency
i_q_valid	TVALID	in
i_q_ready	TREADY	out
i_q	TDATA	in [31:0]

i_q_filtered

AXI-Stream slave - Filtered demodulated I/Q sample data channel.

Physical Port	Logical Port	Direction	Dependency
i_q_filtered_valid	TVALID	in
i_q_filtered_ready	TREADY	out
i_q_filtered	TDATA	in [31:0]

dma_wr

FIFO Write Interface master - Low-level SPI bus interface that is controlled by peripheral.

Physical Port	Logical Port	Direction	Dependency
dma_wr_en	EN	out
dma_wr_data	DATA	out [31:0]
dma_wr_overflow	OVERFLOW	in
dma_wr_xfer_req	XFER_REQ	in

Ports

Physical Port	Direction	Dependency	Description
clk	in		Clock - All other signals are synchronous to this clock. Bus phase_data_data_filtered_i_q_i_q_filtered_dma_wr is synchronous to this clock domain.
resetn	in		Synchronous active low reset - Resets the internal state machine of the core.
overflow	out		Output - The overflow signal is asserted if a overflow on the DMA interface is detected.
dma_wr_sync	out
channel_enable	in [13:0]		Input - Data channel enable sequencer output enable.
processing_resetn	out		Output - Reset signal for the processing pipeline Bus phase_data_data_filtered_i_q_i_q_filtered_dma_wr is synchronous to this reset signal.

Detailed Description

The CN0363 DMA sequencer core acts as a link between the CN0363 processing pipeline and the connected DMA controller. On one side it accepts data from the processing pipeline and on the other side it sends the data to the DMA controller. The core is only active when the DMA controller signals that it is waiting for data, when it is inactive it also asserts the processing_resetn signal to keep the processing pipeline in reset. Since the DMA is running at a much faster clock than the output data rate from the processing pipeline the different channels are time-division-multiplexed and send one by one to the DMA controller over the dma_wr interface.

When active, the core cycles through the input channels in the following order:

1. phase (Reference channel)

2. data (Reference channel)

3. data_filtered (Reference channel)

4. i_q, I component (Reference channel)

5. i_q, Q component (Reference channel)

6. i_q_filtered, I component (Reference channel)

7. i_q_filtered, Q component (Reference channel)

8. phase (Sample channel)

9. data (Sample channel)

10. data_filtered (Sample channel)

11. i_q, I component (Sample channel)

12. i_q, Q component (Sample channel)

13. i_q_filtered, I component (Sample channel)

14. i_q_filtered, Q component (Sample channel)

Each of these has a corresponding bit in the channel_enable and only if the bit is set, the channel is sent to the dma_wr interface, otherwise it is discarded. This allows an application to select which data channels it wants to capture.

Software Support

• Linux device driver at drivers/iio/adc/ad7173.c

• Linux device driver documentation at Linux Device Drivers

• No-OS device driver at drivers/adc/ad717x

• No-OS device driver documentation at AD717X No-OS Software Drivers

References

• HDL IP Core at library/cn0363/cn0363_dma_sequencer

• HDL project at projects/cn0363

• HDL project documentation at CN0363 HDL project

• CN0363

• AD7175-2

• Zynq-7000 SoC Overview

• Zynq-7000 SoC Packaging and Pinout