PLUTO HDL Project

Overview

The ADALM-PLUTO Active Learning Module (PlutoSDR) is an easy to use tool available from Analog Devices Inc. (ADI) that can be used to introduce fundamentals of Software Defined Radio (SDR) or Radio Frequency (RF) or Communications as advanced topics in electrical engineering in a self or instructor lead setting.

Based on the AD9363, it offers one receive channel and one transmit channel which can be operated in full duplex, capable of generating or measuring RF analog signals from 325 to 3800 MHz, at up to 61.44 Mega Samples per Second (MSPS) with a 20 MHz bandwidth. The PlutoSDR is completely self-contained, fits nicely in a shirt pocket or backpack, and is entirely USB powered with the default firmware. With support for OS X™, Windows™ and Linux™, it allows exploration and understanding of RF systems no matter where the user is or when.

The 2nd Rx/Tx channel internal to the rev D is not test during production test. If it works - bonus! If it doesn’t work, Pluto is only advertised as a 1 Rx, 1 Tx radio, and that is guaranteed/production tested on each unit - and that is what you received.

Supported boards

Supported devices

Block design

In both receive and transmit directions, complex I and Q signals are generated for each RF.

Block diagram

The data path and clock domains are depicted in the below diagram.

PLUTO block diagram

Clock scheme

The clocks are managed by the device and are software programmable. Please refer to the device data sheet for the various clocks within the device.

The board provides a 40MHz crystal for the AD9363. For more details about the clocking, check the AD9361 Reference Manual, page 14, “Reference Clock Requirements”.

Configuration modes

The AD9361 IP in this HDL project is configured to work only in CMOS interface; it supports two configuration modes:

  • 2R2T - 2x receive and 2x transmit RF channels

  • 1R1T - 1x receive and 1x transmit RF channel

Both support only the dual port half duplex operating mode. The maximum data rate (for combined I and Q words) is 61.44MSPS in DDR. For more details about these modes, check the AD9361 Reference Manual, Table 48 “Maximum Data Rates and Signal Bandwidths”.

The following are the parameters of this project that can be configured:

  • TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1

  • TDD_CHANNEL_CNT

  • TDD_SYNC_WIDTH

  • TDD_SYNC_INT

  • TDD_SYNC_EXT

  • TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added

  • Check out this guide on more details regarding these parameters: AXI TDD

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

Zynq

axi_ad9361_adc_dma

0x7C40_0000

axi_ad9361_dac_dma

0x7C42_0000

axi_spi

0x7C43_0000

axi_tdd_0

0x7C44_0000

axi_ad9361

0x7902_0000

SPI connections

The SPI signals are controlled by a separate AXI based SPI core.

SPI type

SPI manager instance

SPI subordinate

CS

PS

SPI 0

AD9361

0

GPIOs

The device control and monitor signals are interfaced to a GPIO module.

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

pl_muxout

OUT

17

71

phaser_enable

IN

14

68

gpio_resetb

INOUT

13

67

gpio_en_agc

INOUT

12

66

gpio_ctl[3:0]

INOUT

11:8

65:62

gpio_status[7:0]

INOUT

7:0

61:54

Note

The user can select the Programmable Logic GPIO operation through the phaser_enable software-controlled pin.

The phaser_enable pin defaults to 0, selecting the Pluto functionality. If set to 1, the GPIOs switch to Phaser functionality.

Processor System (PS)

Zynq 7010 Pin

Zynq Pin Name

S chematic Net

PCB Test Point

Pluto Funct ionality

Phaser Funct ionality

K13

IO_L1 0P_T1_34

PL_GPIO0

L10P

SPI MOSI

TXDATA

M12

IO _L12N_T1 _MRCC_34

PL_GPIO1

L12N

SPI MISO

BURST

R10

IO_L2 4N_T3_34

PL_GPIO2

L24N

SPI CLKO

MUXOUT

N14

IO_L 7N_T1_34

PL_GPIO3

L7N

IIC SDA

IIC SDA

M14

IO_L9N_T 1_DQS_34

PL_GPIO4

L9N

IIC SCL

IIC SCL

Processor System (PS)

Zynq 7010 Pin

Zynq Pin Name

Schematic Net

PCB Test Point

D8

PS_MIO0_500

PS_GPIO0

MIO0

B10

PS_MIO11_500

PS_GPIO1

MIO10

D6

PS_MIO10_500

PS_GPIO2

MIO11

B5

PS_MIO9_500

PS_GPIO3

MIO09

C13

PS_MIO53_501

PS_GPIO4

MIO53

D13

PS_MIO49_501

PS_GPIO5

MIO49

B12

PS_MIO48_501

PS_GPIO6

MIO48

Interrupts

Below are the Programmable Logic interrupts used in the project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad9361_adc_dma

13

57

89

axi_ad9361_dac_dma

12

56

88

axi_spi

11

55

87

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Go to the hdl/projects/pluto location and run the make command.

Linux/Cygwin/WSL

~$

cd hdl/projects/pluto

~/hdl/projects/pluto$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.