AD9083-EVB HDL Project

Overview

The AD9083_EVB reference design is a processor-based embedded system. The design consists of a receive chain; the receive chain transports the captured samples from ADC to the system memory (DDR). The AD9083-EVB evaluation board includes all the support circuitry required to operate the AD9083 in various modes and configurations.

The AD9083 is a 16-bit, 16 channel with 125 MHz bandwidth per channel (2 GSPS total) analog-to-digital converter (ADC) featuring an on-chip programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use. The digital outputs are designed to use the JESD204B standard, in subclass 1 or 0. The current HDL design supports only subclass 1 operations.

Supported boards

EVAL-AD9083

Supported devices

AD9083

Supported carriers

Evaluation board	Carrier	FMC slot
AD9083-EVB	A10SoC	FMCA using FMC extender
	ZCU102	FMC HPC0

Block design

The digital outputs are designed to use the JESD204B standard, in subclass 1 or 0. The current HDL design supports only subclass 1 operations (deterministic latency being a system requirement).

Block diagram

The data path and clock domains are depicted in the below diagrams:

ZCU102

A10SoC

Configuration modes

The following are the parameters of this project that can be configured, followed by the default configuration:

RX_JESD_L: number of lanes per link; by default 4
RX_JESD_M: number of converters per link; by default 16
RX_JESD_S: number of samples per frame; by default 1

Other JESD204B output configuration modes can be found in the AD9083 data sheet, at Table 24.

Clock scheme

The AD9083 PLL reference clock, the FPGA reference clock and the FPGA global clock are provided by the on-board AD9528 JESD204B clock generator.

The device clock and the link clock have different sources, and in this case, the link clock is double the device clock.

\begin{array}{r} \begin{aligned} L a n e R a t e & = \frac{I Q S a m p l e R a t e * M * N P * \frac{10}{8}}{L} = 10 G b p s \\ L i n k C l o c k & = \frac{L a n e R a t e}{40} = 250 M b p s \\ D e v i c e C l o c k & = \frac{L i n k C l o c k}{2} = 125 M b p s \end{aligned} \end{array}

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	ZynqMP	A10Soc
rx_ad9083_tpl_core	0x84A0_0000	0x0005_0000
axi_ad9083_rx_xcvr	0x84A6_0000	0x0004_8000
axi_ad9083_rx_jesd	0x84AA_0000	0x0004_0000
axi_ad9083_rx_dma	0x9C40_0000	0x0004_C000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	AD9083	0
PS	SPI 0	AD9528	1

GPIOs

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO	Software GPIO
	(from FPGA view)		Zynq-7000	Zynq MP
refsel	INOUT	34	181:150	205:174
rstb	INOUT	33	149:118	173:142
pwdn	INOUT	32	86	110

Note

For A10SoC project, the GPIO numbers coincide with the HDL GPIO EMIO number (column 3 from the table).

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux ZynqMP	Actual ZynqMP	A10SoC
axi_ad9083_rx_dma	13	109	141	—
axi_ad9083_rx_jesd	12	108	140	—
axi_ad9083_dma	12	—	—	31
ad9083_jesd204	11	—	—	32

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the hdl/projects/$eval_board/$carrier location and run the make command.

Linux/Cygwin/WSL

Building the project on ZCU102 without parameters, will use the default configuration, meaning L = 4, M = 16 and L = 1.

~$

cd hdl/projects/ad9083_evb/zcu102

~/hdl/projects/ad9083_evb/zcu102$

make

Example of running the make command with parameters:

~$

cd hdl/projects/ad9083_evb/zcu102

~/hdl/projects/ad9083_evb/zcu102$

make RX_JESD_L=4 RX_JESD_M=16

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

make RX_JESD_L=4 RX_JESD_M=16

then the folder name will be:

RXL4_RXM16 because of truncation of some keywords so the name will not exceed the limits of the Operating System (JESD, LANE, etc. are removed) of 260 characters.

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

AD9083-EVB HDL project source code

IP name	Source code link	Documentation link
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility
UTIL_ADCFIFO	library/util_adcfifo *	—
UTIL_ADXCVR	library/xilinx/util_adxcvr **	UTIL_ADXCVR core for AMD Xilinx devices
AXI_ADXCVR	library/xilinx/axi_adxcvr **	AMD Xilinx Devices
AXI_JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
JESD204_TPL_ADC	library/jesd204/ad_ip_jesd204_tpl_adc	ADC JESD204B/C Transport Peripheral

Note

* - used only in A10SoC project
** - used only in ZCU102 project

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.