AD—- HDL Project (template)

Overview

Supported boards

EVAL-AD9467

Supported devices

Supported carriers

Evaluation board	Carrier	FMC slot
EVAL-AD9081	A10SoC	FMCA
	VCK190	FMC0
	VCU118	FMC+
	VCU128	FMC+
	ZCU102	FMC HPC0
	ZC706	FMC HPC

Evaluation board	Carrier	FMC slot
EVAL-AD9082	VCK190	FMC0
	VCU118	FMC+
	ZCU102	FMC HPC0
	ZC706	FMC HPC

Block design

Block diagram

If the project has multiple ways of configuration, then make subsections to this section and show the default configuration and some other popular modes.

The data path and clock domains are depicted in the below diagram:

Configuration modes

The following are the parameters of this project that can be configured:

JESD_MODE: used link layer encoder mode
- 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical Layer
- 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical Layer
RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA)
TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE)
REF_CLK_RATE: the rate of the reference clock
[RX/TX]_JESD_M: number of converters per link
[RX/TX]_JESD_L: number of lanes per link
[RX/TX]_JESD_S: number of samples per frame
[RX/TX]_JESD_NP: number of bits per sample
[RX/TX]_NUM_LINKS: number of links
[RX/TX]_TPL_WIDTH
TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1
SHARED_DEVCLK
TDD_CHANNEL_CNT
TDD_SYNC_WIDTH
TDD_SYNC_INT
TDD_SYNC_EXT
TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added
[RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)
[ADC/DAC]_DO_MEM_TYPE
Check out this guide on more details regarding these parameters: AXI TDD

Clock scheme

External clock source AD-SYNCHRONA14-EBZ
SYSREF clocks are LVDS
ADCCLK and REFCLK are LVPECL

Only the channels presented in the clocking selection are relevant. For the rest, you can either disable them or just put a divided frequency of the source clock.

Limitations

The design has one JESD receive chain with 4 lanes at rate of 13Gbps. The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The link operates in Subclass 1.

The link is set for full bandwidth mode and operate with the following parameters:

Deframer paramaters: L=4, M=2, F=1, S=1, NP=16

SYSREF - 5.078125 MHZ
REFCLK - 325MHz (Lane Rate/40)
DEVICECLK - 325 MHz
ADCCLK - 1300MHz
JESD204B Lane Rate - 13Gbps

The transport layer component presents on its output 128 bits at once on every clock cycle, representing 4 samples per converter. The two receive chains are merged together and transferred to the DDR with a single DMA.

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT, some IPs are instantiated and some are not.

Check-out the table below to find out the conditions.

Instance	Depends on parameter	Zynq/Microblaze	ZynqMP	Versal
axi_mxfe_rx_xcvr	$INTF_CFG!=”TX” & $ADI_PHY_SEL==1	0x44A6_0000	0x84A6_0000	0xA4A6_00000
rx_mxfe_tpl_core	$INTF_CFG!=”TX”	0x44A1_0000	0x84A1_0000	0xA4A1_00000
axi_mxfe_rx_jesd	$INTF_CFG!=”TX”	0x44A9_0000	0x84A9_0000	0xA4A9_00000
axi_mxfe_rx_dma	$INTF_CFG!=”TX”	0x7C42_0000	0x9C42_0000	0xBC42_00000
mxfe_rx_data_offload	$INTF_CFG!=”TX”	0x7C45_0000	0x9C45_0000	0xBC45_00000
axi_mxfe_tx_xcvr	$INTF_CFG!=”RX” & $ADI_PHY_SEL==1	0x44B6_0000	0x84B6_0000	0xA4B6_00000
tx_mxfe_tpl_core	$INTF_CFG!=”RX”	0x44B1_0000	0x84B1_0000	0xA4B1_00000
axi_mxfe_tx_jesd	$INTF_CFG!=”RX”	0x44B9_0000	0x84B9_0000	0xA4B9_00000
axi_mxfe_tx_dma	$INTF_CFG!=”RX”	0x7C43_0000	0x9C43_0000	0xBC43_00000
mxfe_tx_data_offload	$INTF_CFG!=”RX”	0x7C44_0000	0x9C44_0000	0xBC44_00000
axi_tdd_0	$TDD_SUPPORT==1	0x7C46_0000	0x9C46_0000	0xBC46_00000

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate

SPI connections

SPI type	SPI manager instance	SPI subordinate
PS	SPI 0	ADXYZT
PS	SPI 1	AD0000
PL	axi_spi_bus_1	AD23456

GPIOs

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO	Software GPIO
	(from FPGA view)		Zynq-7000	Zynq MP
signal_name[31:0]	IN/OUT/INOUT	127:96	181:150	205:174
signal_name[31:0]	IN/OUT/INOUT	95:64	149:118	173:142
signal_name[31:0]	IN/OUT/INOUT	63:32	117:86	141:110

Interrupts

Below are the Programmable Logic interrupts used in this project.

You have many ways of writing this table: as a list-table or really to draw it. Take a look in the .rst of this page to see how they’re written and which suits best your case.

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP
—	15	59	91	111	143
—	14	58	90	110	142
—	13	57	89	109	141
—	12	56	88	108	140
—	11	55	87	107	139
—	10	54	86	106	138
—	9	53	85	105	137
—	8	52	84	104	136
—	7	36	68	96	128
—	6	35	67	95	127
—	5	34	66	94	126
—	4	33	65	93	125
—	3	32	64	92	124
—	2	31	63	91	123
—	1	30	62	90	122
—	0	29	61	89	121

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP	S10SoC	Linux Cyclone V	Actual Cyclone V
—	15	59	91	111	143	32	55	87
—	14	58	90	110	142	31	54	86
—	13	57	89	109	141	30	53	85
—	12	56	88	108	140	29	52	84
—	11	55	87	107	139	28	51	83
—	10	54	86	106	138	27	50	82
—	9	53	85	105	137	26	49	81
—	8	52	84	104	136	25	48	80
—	7	36	68	96	128	24	47	79
—	6	35	67	95	127	23	46	78
—	5	34	66	94	126	22	45	77
—	4	33	65	93	125	21	44	76
—	3	32	64	92	124	20	43	75
—	2	31	63	91	123	19	42	74
—	1	30	62	90	122	18	41	73
—	0	29	61	89	121	17	40	72

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the hdl/projects/$eval_board/$carrier location and run the make command.

Linux/Cygwin/WSL

Example of running the make command without parameters (using the default configuration):

~$

cd hdl/projects/ad9081_fmca_ebz/zcu102

~/hdl/projects/ad9081_fmca_ebz/zcu102$

make

Example of running the make command with parameters:

~$

cd hdl/projects/ad9081_fmca_ebz/a10soc

~/hdl/projects/ad9081_fmca_ebz/a10soc$

make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16

The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. Where a cell contains a — (dash) it means that the parameter doesn’t exist for that project (ad9081_fmca_ebz/$carrier or ad9082_fmca_ebz/$carrier).

Default values of the make parameters for AD9082-FMCA-EBZ

Parameter	Default value of the parameters depending on carrier
Parameter	VCK190	VCU118	ZC706	ZCU102
JESD_MODE	64B66B	8B10B	8B10B*	8B10B*
RX_LANE_RATE	24.75	15	10	15
TX_LANE_RATE	24.75	15	10	15
REF_CLK_RATE	375	—	—	—
RX_JESD_M	4	4	8	4
RX_JESD_L	8	8	4	8
RX_JESD_S	4	1	1	1
RX_JESD_NP	12	16	16	16
RX_NUM_LINKS	1	1	1	1
RX_TPL_WIDTH	—	—	—	{}
TX_JESD_M	4	4	8	4
TX_JESD_L	8	8	4	8
TX_JESD_S	8	1	1	1
TX_JESD_NP	12	16	16	16
TX_NUM_LINKS	1	1	1	1
TX_TPL_WIDTH	—	—	—	{}
RX_KS_PER_CHANNEL	64	64	—	—
TX_KS_PER_CHANNEL	64	64	—	—

Legend

* — for this carrier only the 8B10B mode is supported

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16

then the folder name will be:

RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16 because of truncation of some keywords so the name will not exceed the limits of the Operating System (JESD, LANE, etc. are removed) of 260 characters.

A more comprehensive build guide can be found in the Build an HDL project user guide.

Software considerations

ADC - crossbar config * EXAMPLE *

Due to physical constraints, Rx lanes are reordered as described in the following table.

e.g physical lane 2 from ADC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.

ADC phy Lane	FPGA Rx lane / Logical Lane
0	2
1	0
2	7
3	6
4	5
5	4
6	3
7	1

DAC - crossbar config * EXAMPLE *

Due to physical constraints, Tx lanes are reordered as described in the following table:

e.g physical lane 2 from DAC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.

DAC phy Lane	FPGA Tx lane / Logical Lane
0	0
1	2
2	7
3	6
4	1
5	5
6	4
7	3

Resources

Systems related

Links to the Quick start guides, to the pages where the hardware changes are specified in detail, etc. in the form of a table as the one below

[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide
Here you can find all the quick start guides on wiki documentation [Wiki] AD9081/AD9082/AD9986/AD9988 Quick Start Guides

Here you can find the quick start guides available for these evaluation boards:

Evaluation board	Zynq-7000	Zynq UltraScale+ MP	Microblaze	Versal	Arria 10
AD9081/AD9082-FMCA-EBZ	ZC706	ZCU102	VCU118	VCK190/VMK180	A10SoC

Other relevant information

HDL related

Link to the project source code
Table like the one below. Must have as first IP (if it exists) the IP that was created with this project (i.e., axi_ad9783). If there isn’t, then to be taken in the order they are written in the Makefile of the project, stating the source code link in a column and the documentation link in another column
Other relevant information

IP name	Source code link	Documentation link
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility
UTIL_UPACK2	library/util_pack/util_upack2	Channel UPACK Utility
UTIL_ADXCVR for AMD	library/xilinx/util_adxcvr	UTIL_ADXCVR core for AMD Xilinx devices
AXI_ADXCVR for Intel	library/intel/axi_adxcvr	Intel Devices
AXI_ADXCVR for AMD	library/xilinx/axi_adxcvr	AMD Xilinx Devices
AXI_JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
AXI_JESD204_TX	library/jesd204/axi_jesd204_tx	JESD204B/C Link Transmit Peripheral
JESD204_TPL_ADC	library/jesd204/ad_ip_jesd204_tpl_adc	ADC JESD204B/C Transport Peripheral
JESD204_TPL_DAC	library/jesd204/ad_ip_jesd204_tpl_dac	DAC JESD204B/C Transport Peripheral

SPI Engine Framework documentation

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP
—	15	59	91	111	143
—	14	58	90	110	142
—	13	57	89	109	141
—	12	56	88	108	140
—	11	55	87	107	139
—	10	54	86	106	138
—	9	53	85	105	137
—	8	52	84	104	136
—	7	36	68	96	128
—	6	35	67	95	127
—	5	34	66	94	126
—	4	33	65	93	125
—	3	32	64	92	124
—	2	31	63	91	123
—	1	30	62	90	122
—	0	29	61	89	121

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP	S10SoC	Linux Cyclone V	Actual Cyclone V
—	15	59	91	111	143	32	55	87
—	14	58	90	110	142	31	54	86
—	13	57	89	109	141	30	53	85
—	12	56	88	108	140	29	52	84
—	11	55	87	107	139	28	51	83
—	10	54	86	106	138	27	50	82
—	9	53	85	105	137	26	49	81
—	8	52	84	104	136	25	48	80
—	7	36	68	96	128	24	47	79
—	6	35	67	95	127	23	46	78
—	5	34	66	94	126	22	45	77
—	4	33	65	93	125	21	44	76
—	3	32	64	92	124	20	43	75
—	2	31	63	91	123	19	42	74
—	1	30	62	90	122	18	41	73
—	0	29	61	89	121	17	40	72

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP
—	15	59	91	111	143
—	14	58	90	110	142
—	13	57	89	109	141
—	12	56	88	108	140
—	11	55	87	107	139
—	10	54	86	106	138
—	9	53	85	105	137
—	8	52	84	104	136
—	7	36	68	96	128
—	6	35	67	95	127
—	5	34	66	94	126
—	4	33	65	93	125
—	3	32	64	92	124
—	2	31	63	91	123
—	1	30	62	90	122
—	0	29	61	89	121

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP	S10SoC	Linux Cyclone V	Actual Cyclone V
—	15	59	91	111	143	32	55	87
—	14	58	90	110	142	31	54	86
—	13	57	89	109	141	30	53	85
—	12	56	88	108	140	29	52	84
—	11	55	87	107	139	28	51	83
—	10	54	86	106	138	27	50	82
—	9	53	85	105	137	26	49	81
—	8	52	84	104	136	25	48	80
—	7	36	68	96	128	24	47	79
—	6	35	67	95	127	23	46	78
—	5	34	66	94	126	22	45	77
—	4	33	65	93	125	21	44	76
—	3	32	64	92	124	20	43	75
—	2	31	63	91	123	19	42	74
—	1	30	62	90	122	18	41	73
—	0	29	61	89	121	17	40	72