ADMX100X-EVB HDL project

The EVAL-ADMX1001 and EVAL-ADMX1002 modules are ultra-low-distortion, low-noise signal generators. They support output frequencies up to 40 kHz when the digital pre-distortion (DPD) algorithm is disabled, and up to 20 kHz with DPD enabled while maintaining a typical total harmonic distortion (THD) of −130 dB at 1 kHz. The ADMX1001 includes a built-in acquisition channel that enables simultaneous generation and capture of differential signals, making it ideal for characterization and closed-loop evaluation of high-performance ADCs, audio converters, and precision sensing systems. The integrated DPD algorithm minimizes distortion typically introduced by DAC and amplifier stages, enabling the generation of extremely clean test signals for precision measurement applications. The ADMX1002 focuses solely on high-fidelity signal generation, providing a streamlined solution for setups where local signal acquisition is not required.

The HDL reference design implements both the TX signal generation path and the RX acquisition path. The RX path uses an ADAQ7768-1 precision ADC, enabling simultaneous signal generation and capture on the ADMX1001.

This project has a SPI Engine instance to control and acquire data from the ADAQ7768-1 24-bit precision ADC. This instance provides support for capturing continuous samples at the maximum sample rate of 256 kSPS.

Supported boards

Supported devices

Supported carriers

Evaluation board	Carrier	FMC slot
EVAL-ADMX1001	ZedBoard	FMC LPC
EVAL-ADMX1002	ZedBoard	FMC LPC

Block design

The reference design uses the SPI Engine Framework to interface with the ADAQ7768-1 precision ADC on the RX acquisition path. The SPI Engine Offload module is used to capture continuous samples at the maximum sample rate of 256 kSPS, triggered by the DRDY (data ready) signal of the ADAQ7768-1.

Warning

The VADJ for the Zedboard must be set to 3.3V.

Block diagram

The data path and clock domains are depicted in the below diagram:

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	CS_FPGA	0
PS	SPI 0	CS_DAC	1
PL	axi_spi_engine	ADAQ7768-1	0

GPIOs

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
ACQ_DRDY	IN	43	97
ACQ_RESET	OUT	42	96
ACQ_SYNQ_IN_FMC	OUT	41	95
ADMX100X_TRIG	IN	40	94
ADMX100X_DAC_LDAC	OUT	39	93
ADMX100X_CAL	IN	38	92
ADMX100X_VALID	OUT	37	91
ADMX100X_READY	OUT	36	90
ADMX100X_EN	OUT	35	89
ADMX100X_SYNC_MODE	IN	34	88
ADMX100X_RESET	OUT	33	87
ADMX100X_OT	OUT	32	86

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at CPU/Memory interconnects addresses).

Instance	Zynq
spi_adaq77681_axi_regmap	0x44A0_0000
axi_adaq77681_dma	0x44A3_0000
spi_clkgen	0x44A7_0000

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_adaq77681_dma	13	57	89
spi_adaq77681	12	56	88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Linux/Cygwin/WSL

Building the ZedBoard project:

~$

cd hdl/projects/admx100xevb/zed

~/hdl/projects/admx100xevb/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

ADMX100X-EVB HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—

SPI Engine Framework documentation

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.