LTC2378-FMC HDL project

Overview

The LTC23xx family consists of low noise, low power, high speed successive approximation register (SAR) ADCs with resolutions of 16-bit, 18-bit and 20-bit and maximum sampling rates from 250 kSPS to 2 MSPS. Operating from a 2.5V or 5V supply, these ADCs feature either fully differential or pseudo-differential input configurations with VREF ranging from 2.5V to 5.1V. The LTC2338-18 is a special variant operating from a single 5V supply with a ±10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range.

All devices in the family feature a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast throughput with no cycle latency makes the LTC23xx family ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The devices automatically power down between conversions, leading to reduced power dissipation that scales with the sampling rate.

The LTC2376-16, LTC2376-18, LTC2376-20, LTC2377-16, LTC2377-18, LTC2377-20, LTC2378-16, LTC2378-18, LTC2378-20, LTC2379-18, LTC2380-16 variants feature a unique digital gain compression (DGC) function, which eliminates the driver amplifier’s negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling function that maps zero-scale code from 0V to 0.1 x VREF and full-scale code from VREF to 0.9 x VREF. For a typical reference voltage of 5V, the full-scale input range is now 0.5V to 4.5V, which provides adequate headroom for powering the driving amplifier from a single 5.5V supply.

Applications:

• Medical Imaging

• High Speed Data Acquisition

• Portable or Compact Instrumentation

• Industrial Process Control

• Low Power Battery-Operated Instrumentation

• ATE

Supported boards

TO BE ADDED

Supported devices

• LTC2378-20

• LTC2377-20

• LTC2376-20

• LTC2370-16

• LTC2369-18

• LTC2368-16/18

• LTC2367-16/18

• LTC2364-16/18

• LTC2380-16

• LTC2379-18

• LTC2378-16/18

• LTC2377-16/18

• LTC2376-16/18

• LTC2338-18

Supported carriers

• ZedBoard on FMC slot

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq
spi_ltc2378_axi_regmap	0x44A0_0000
ltc2378_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
ltc2378_trigger_gen	0x44B0_0000

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL	iic_main	axi_iic_main	0x4160_0000	—

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	axi_spi_engine	ltc2378	0

GPIOs

The Software GPIO number is calculated as follows:

• Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
ltc2378_dcgn	INOUT	33	87
ltc2378_chain	INOUT	32	86

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
ltc2378_dma	13	57	89
spi_ltc2378	12	56	88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

~$

cd hdl/projects/ltc2378_fmc/zed

~/hdl/projects/ltc2378_fmc/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Hardware related

• Product datasheets:

  • LTC2378-20

  • LTC2377-20

  • LTC2376-20

  • LTC2370-16

  • LTC2369-18

  • LTC2368-16/18

  • LTC2367-16/18

  • LTC2364-16/18

  • LTC2380-16

  • LTC2379-18

  • LTC2378-16/18

  • LTC2377-16/18

  • LTC2376-16/18

  • LTC2338-18

HDL related

• LTC2378_FMC HDL project source code

IP name	Source code link	Documentation link
AD_EDGE_DETECT	library/common/ad_edge_detect.v	—
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C-MIXER	library/util_i2c_mixer	—

• SPI Engine Framework documentation

Software related

TO BE ADDED

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.