AD488X-FMC-EVB HDL project

Overview

The EVAL-AD4880-FMC is designed to demonstrate the AD4880 performance.

The AD488X-FMC-EVB HDL project supports the following AD4880 features:

• Single/Dual lane DDR data capture

• Self synchronization using the fixed pattern and bit-slip feature

• Capturing digital averaging filter with up to 2^10 decimation

• Analog-to-digital converter (ADC) configuration via serial peripheral interface (SPI)

• Sampling rate capability between 1.25 MSPS and 40 MSPS

• Synchronized capture between the channels

Supported boards

• EVAL-AD4880-FMC

Supported devices

• AD4880

Supported carriers

Evaluation board	Carrier	FMC slot
EVAL-AD4880-FMC	ZedBoard	FMC-LPC

Block design

Warning

The VADJ for the Zedboard must be set to 2.5V.

Block diagram

The data path and clock domains are depicted in the below diagram:

Clock scheme

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at HDL Architecture).

Instance	Zynq/Microblaze
axi_ad4080_adc_a	0x44A0_0000
axi_ad4080_adc_b	0x44A1_0000
axi_ad4880_dma	0x44A3_0000
ad4080_b_spi	0x44A7_0000
ad408x_clock_monitor	0x44A8_0000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	AD4880_A	0
PL	ad4080_b_spi	AD4880_B	0
PS	SPI 1	AD9508	0
PS	SPI 1	ADF4350	1

GPIOs

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO	Software GPIO
	(from FPGA view)		Zynq-7000	Zynq MP
adcb_gpio3_fmc	OUT	39	93	117
adcb_gpio2_fmc	OUT	38	92	116
ad9508_sync	OUT	37	91	115
pwrgd	IN	36	90	114
adf435x_lock	IN	35	89	113
adca_gpio3_fmc	INOUT	34	88	112
adca_gpio2_fmc	INOUT	33	87	111

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ad4880_dma	13	57	89
ad4080_b_spi	10	54	86

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad488x_fmc_evb/zed

~/hdl/projects/ad488x_fmc_evb/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

Systems related

• UG-2214, User Guide | EVAL-AD4880

Hardware related

• Product datasheet: AD4880

HDL related

• AD488x-FMC-EVB HDL project source code

IP name	Source code link	Documentation link
AXI_AD408X	library/axi_ad408x	AXI AD408x
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_CLOCK_MONITOR	library/axi_clock_monitor	AXI Clock Monitor
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility

Software related

• Python support:

  • PyADI-IIO documentation

  • PyADI-IIO example

  • PyADI-IIO class

  • AD4880-FMC-EVB Linux device tree zynq-zed-adv7511-ad4880.dts

  • AD4880 Linux driver ad4080.c

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.