Generic JESD204 block designs

Using the generic building blocks from the ADI IP library, together with the JESD framework, parametrizable block designs can be built to interface ADI ADCs and DACs in various JESD modes.

Generic TX path

The following diagram presents a generic JESD TX path from the Application Layer to the FPGA boundary. The application layer is connected to the TX path through the DAC Transport Layer, which for each converter it accepts a data beat on every cycle. The width of data beat is defined by the SPC and NP parameter.

SPC represents the number of samples per converter per data clock cycle. SPC must be a natural number (greater than one and a whole number).

Generic JESD204 TX path

On each clock cycle, the Link layer accepts 32 bits per every lane as a constraint from the physical layer that is configured to 32-bit mode. This means that for each clock cycle, the application layer must provide enough samples for each converter such that the Transport Layer can fill 32 bits of data for each lane.

Due to this constraint, the following equation must hold:

L * 32 = M * NP * SPC

In such designs, the following constraints apply to the Transport Layer:

  • F = {1, 2, 4}

  • NP = {8, 16}

Important

Some general rules that always should hold:

  • LaneRate = SampleRate * (10/8) * (M/L) * NP

  • SampleRate = DAC_rate/Total_interpolation

  • Link Clock = Lane Rate / 40

  • If OUTDIV_CLK is used: Link Clock = (RefClock)/((OutClkSel == 4)? 2 : (OutClkSel == 3)? 1 : 1)

Where:

  • M - “adi,converters-per-device”, device tree property from “axi-jesd204-tx” node

  • L - number of lanes per link, parameter of JESD IP

  • NP - “adi,bits-per-sample” device tree property from “axi-jesd204-tx” node

  • RefClock - reference clock for the transceivers

  • SampleRate - rate of the samples that feeds the JESD link

  • DAC_rate - DAC raw sample rate after interpolation

  • Total_interpolation - product of selected interpolations on the datapath, e.g: DAC_interpolation * Channel_interpolation

  • OutClkSel - “adi,out-clk-select” device tree property from XCVR node

More information on the DAC Transport Layer can be found in DAC JESD204B/C Transport Peripheral page.

The Link layer consists of L number of lanes which form the link. More information on the TX Link layer can be found in JESD204B/C Link Transmit Peripheral page.

Generic RX path

The following diagram presents a generic JESD RX path from the Application Layer to the FPGA boundary. The Application Layer is connected to the RX path through the ADC Transport Layer, which for each converter generates a data beat on every cycle. The width of data beat is defined by the SPC and NP parameter. SPC represents the number of samples per converter per data clock cycle. SPC must be a natural number (greater than one and a whole number).

Generic JESD204 RX path

On each clock cycle, the Link layer generates 32 bits per every lane as it is constrained from the Physical Layer that is configured to 32-bit mode. This means that for each clock cycle, the Application Layer must accept enough samples for each converter so the Transport Layer use 32 bits of data from each lane.

In such designs, the following constraints apply to the Transport Layer:

  • F = {1, 2, 4}

  • NP = {8, 16}

More information on the ADC Transport layer can be found in ADC JESD204B/C Transport Peripheral page.

The Link layer consists from L number of lanes which form the link. More information on the RX Link layer can be found in JESD204B/C Link Receive Peripheral page.

JESD204 modes with F=8

In a period of LinkClk, the Link layer always handles 32 bits per lane. The Transport Layer running at a same clock rate can fill the 32 bits with frames of 1,2 or 4 bytes.

However, for a link with L=1, M=4, NP=16 the minimum number of bytes per frame that must be supported is 8 (F=8).