Corundum Ethernet Core for VCU118

The Corundum Ethernet Core is used by the Corundum Network Stack. This Ethernet Core is specific to the VCU118 FPGA board and encompasses the Ethernet physical layer and other auxiliary structures such as SPI and I2C that are required by the Corundum system. The configurations are based on Corundum NIC reference designs that were adapted to suit the ADI workflow.

Files

Name	Description
library/corundum/ethernet_core/ethernet_core_vcu118.v	Verilog source for the Ethernet Core top module for the VCU118 board.
library/corundum/ethernet_core/ethernet_ip.tcl	TCL script to generate the Vivado IP-integrator project.

Configuration Parameters

Name	Description	Default Value	Choices/Range
TDMA_BER_ENABLE	TDMA BER enable.	0
QSFP_CNT	Qsfp Cnt.	1
IF_COUNT	Interface count.	1
PORTS_PER_IF	Ports per interface.	1
SCHED_PER_IF	Sched Per If.	1
PORT_MASK	Port mask.	0
PORT_COUNT	Port Count.	1
PTP_TS_FMT_TOD	PTP_TS_FMT_TOD.	0
PTP_TS_WIDTH	Ptp Ts Width.	48
TX_TAG_WIDTH	Tx Tag Width.	16
TDMA_INDEX_WIDTH	TDMA index width.	6
PTP_TS_ENABLE	PTP Timestamp Enable.	1
AXIL_CTRL_DATA_WIDTH	AXI4 Lite control data width.	32
AXIL_CTRL_ADDR_WIDTH	AXI4 Lite control address width.	24
AXIL_CTRL_STRB_WIDTH	AXI4 Lite control strobe width.	4
AXIL_IF_CTRL_ADDR_WIDTH	AXI4 Lite interface control address width.	24
AXIL_CSR_ADDR_WIDTH	AXI4 Lite CSR address width.	19
ETH_RX_CLK_FROM_TX	Use TX clock for RX.	0
ETH_RS_FEC_ENABLE	Enable RS FEC.	1
AXIS_DATA_WIDTH	AXI4 Stream data width.	512
AXIS_KEEP_WIDTH	AXI4 Stream keep width.	64
AXIS_TX_USER_WIDTH	AXI4 Stream TX user width.	17
AXIS_RX_USER_WIDTH	AXI4 Stream RX user width.	1

Interface

axis_eth_tx

Physical Port	Logical Port	Direction	Dependency
axis_eth_tx_tdata	TDATA	in [511:0]
axis_eth_tx_tkeep	TKEEP	in [63:0]
axis_eth_tx_tvalid	TVALID	in [0:0]
axis_eth_tx_tready	TREADY	out [0:0]
axis_eth_tx_tlast	TLAST	in [0:0]
axis_eth_tx_tuser	TUSER	in [16:0]

axis_eth_rx

Physical Port	Logical Port	Direction	Dependency
axis_eth_rx_tdata	TDATA	out [511:0]
axis_eth_rx_tkeep	TKEEP	out [63:0]
axis_eth_rx_tvalid	TVALID	out [0:0]
axis_eth_rx_tready	TREADY	in [0:0]
axis_eth_rx_tlast	TLAST	out [0:0]
axis_eth_rx_tuser	TUSER	out [0:0]

ctrl_reg

Physical Port	Logical Port	Direction	Dependency
ctrl_reg_wr_addr	ctrl_reg_wr_addr	in [18:0]
ctrl_reg_wr_data	ctrl_reg_wr_data	in [31:0]
ctrl_reg_wr_strb	ctrl_reg_wr_strb	in [3:0]
ctrl_reg_wr_en	ctrl_reg_wr_en	in
ctrl_reg_wr_wait	ctrl_reg_wr_wait	out
ctrl_reg_wr_ack	ctrl_reg_wr_ack	out
ctrl_reg_rd_addr	ctrl_reg_rd_addr	in [18:0]
ctrl_reg_rd_data	ctrl_reg_rd_data	out [31:0]
ctrl_reg_rd_en	ctrl_reg_rd_en	in
ctrl_reg_rd_wait	ctrl_reg_rd_wait	out
ctrl_reg_rd_ack	ctrl_reg_rd_ack	out

flow_control_tx

Physical Port	Logical Port	Direction	Dependency
eth_tx_enable	tx_enable	in [0:0]
eth_tx_status	tx_status	out [0:0]
eth_tx_lfc_en	tx_lfc_en	in [0:0]
eth_tx_lfc_req	tx_lfc_req	in [0:0]
eth_tx_pfc_en	tx_pfc_en	in [7:0]
eth_tx_pfc_req	tx_pfc_req	in [7:0]

flow_control_rx

Physical Port	Logical Port	Direction	Dependency
eth_rx_enable	rx_enable	in [0:0]
eth_rx_status	rx_status	out [0:0]
eth_rx_lfc_en	rx_lfc_en	in [0:0]
eth_rx_lfc_req	rx_lfc_req	out [0:0]
eth_rx_lfc_ack	rx_lfc_ack	in [0:0]
eth_rx_pfc_en	rx_pfc_en	in [7:0]
eth_rx_pfc_req	rx_pfc_req	out [7:0]
eth_rx_pfc_ack	rx_pfc_ack	in [7:0]

axis_tx_ptp

Physical Port	Logical Port	Direction	Dependency
axis_eth_tx_ptp_ts	ts	out [47:0]
axis_eth_tx_ptp_ts_tag	tag	out [15:0]
axis_eth_tx_ptp_ts_valid	valid	out [0:0]
axis_eth_tx_ptp_ts_ready	ready	in [0:0]

qspi0

Physical Port	Logical Port	Direction	Dependency
qspi_0_dq_i	dq_i	in [3:0]
qspi_0_dq_o	dq_o	out [3:0]
qspi_0_dq_oe	dq_oe	out [3:0]
qspi_0_cs	cs	out

qspi1

Physical Port	Logical Port	Direction	Dependency
qspi_1_dq_i	dq_i	in [3:0]
qspi_1_dq_o	dq_o	out [3:0]
qspi_1_dq_oe	dq_oe	out [3:0]
qspi_1_cs	cs	out

qsfp

Physical Port	Logical Port	Direction	Dependency
qsfp_tx_p	tx_p	out [3:0]
qsfp_tx_n	tx_n	out [3:0]
qsfp_rx_p	rx_p	in [3:0]
qsfp_rx_n	rx_n	in [3:0]
qsfp_modsell	modsell	out [0:0]
qsfp_resetl	resetl	out [0:0]
qsfp_modprsl	modprsl	in [0:0]
qsfp_intl	intl	in [0:0]
qsfp_lpmode	lpmode	out [0:0]
qsfp_gtpowergood	gtpowergood	out [0:0]

i2c

Physical Port	Logical Port	Direction	Dependency
i2c_scl_i	scl_i	in
i2c_scl_o	scl_o	out
i2c_scl_t	scl_t	out
i2c_sda_i	sda_i	in
i2c_sda_o	sda_o	out
i2c_sda_t	sda_t	out

ethernet_ptp_tx

Physical Port	Logical Port	Direction	Dependency
eth_tx_ptp_clk	ptp_clk	out [0:0]
eth_tx_ptp_rst	ptp_rst	out [0:0]
eth_tx_ptp_ts	ptp_ts	in [47:0]
eth_tx_ptp_ts_step	ptp_ts_step	in [0:0]

ethernet_ptp_rx

Physical Port	Logical Port	Direction	Dependency
eth_rx_ptp_clk	ptp_clk	out [0:0]
eth_rx_ptp_rst	ptp_rst	out [0:0]
eth_rx_ptp_ts	ptp_ts	in [47:0]
eth_rx_ptp_ts_step	ptp_ts_step	in [0:0]

Ports

Physical Port	Direction	Dependency	Description
clk	in
rst	in
clk_125mhz	in
rst_125mhz	in
qsfp_drp_clk	in [0:0]
qsfp_drp_rst	in [0:0]
qsfp_mgt_refclk	in [0:0]
qsfp_mgt_refclk_bufg	in [0:0]
qsfp_rst	out [0:0]
eth_tx_clk	out [0:0]		Bus axis_eth_tx_axis_tx_ptp is synchronous to this clock domain.
eth_tx_rst	out [0:0]		Bus axis_eth_tx_axis_tx_ptp is synchronous to this reset signal.
eth_rx_clk	out [0:0]		Bus axis_eth_rx is synchronous to this clock domain.
eth_rx_rst	out [0:0]		Bus axis_eth_rx is synchronous to this reset signal.
fpga_boot	out
qspi_clk	out

References

• HDL IP core at library/corundum/ethernet_core