Corundum Ethernet Core for K26

The Corundum Ethernet Core is used by the Corundum Network Stack. This Ethernet Core is specific to the K26 FPGA board and encompasses the Ethernet physical layer and other auxiliary structures such as SPI and I2C that are required by the Corundum system. The configurations are based on Corundum NIC reference designs that were adapted to suit the ADI workflow.

Files

Name	Description
library/corundum/ethernet_core/ethernet_core_k26.v	Verilog source for the Ethernet Core top module for the K26-based AD-GMSL2ETH-SL evaluation kit.
library/corundum/ethernet_core/ethernet_ip.tcl	TCL script to generate the Vivado IP-integrator project.

Configuration Parameters

Name	Description	Default Value	Choices/Range
IF_COUNT	Interface count.	1
PORTS_PER_IF	Ports per interface.	1
SCHED_PER_IF	Sched Per If.	1
PORT_MASK	Port mask.	0
PORT_COUNT	Port Count.	1
TDMA_BER_ENABLE	Tdma Ber Enable.	0
PTP_PEROUT_COUNT	Ptp Perout Count.	1
PTP_TS_ENABLE	PTP Timestamp Enable.	1
PTP_TS_FMT_TOD	PTP_TS_FMT_TOD.	1
PTP_TS_WIDTH	Ptp Ts Width.	64
TX_TAG_WIDTH	Tx Tag Width.	16
PFC_ENABLE	PFC_ENABLE.	1
LFC_ENABLE	Lfc Enable.	1
ENABLE_PADDING	ENABLE_PADDING.	1
ENABLE_DIC	ENABLE_DIC.	1
MIN_FRAME_LENGTH	MIN_FRAME_LENGTH.	64
XGMII_DATA_WIDTH	Xgmii Data Width.	64
XGMII_CTRL_WIDTH	Xgmii Ctrl Width.	8
AXIS_DATA_WIDTH	Axis Data Width.	64
AXIS_KEEP_WIDTH	Axis Keep Width.	8
AXIS_TX_USER_WIDTH	Axis Tx User Width.	17
AXIS_RX_USER_WIDTH	Axis Rx User Width.	1
AXIL_CTRL_DATA_WIDTH	Axil Ctrl Data Width.	32
AXIL_CTRL_ADDR_WIDTH	Axil Ctrl Addr Width.	24
AXIL_CTRL_STRB_WIDTH	Axil Ctrl Strb Width.	4
AXIL_IF_CTRL_ADDR_WIDTH	Axil If Ctrl Addr Width.	24
AXIL_CSR_ENABLE	AXI4 Lite CSR enable.	0
AXIL_CSR_ADDR_WIDTH	Axil Csr Addr Width.	19
STAT_ENABLE	Stat Enable.	0
STAT_DMA_ENABLE	Stat Dma Enable.	1
STAT_AXI_ENABLE	Stat Axi Enable.	1
STAT_INC_WIDTH	Stat Inc Width.	24
STAT_ID_WIDTH	Stat Id Width.	12

Interface

axis_eth_tx

Physical Port	Logical Port	Direction	Dependency
axis_eth_tx_tdata	TDATA	in [63:0]
axis_eth_tx_tkeep	TKEEP	in [7:0]
axis_eth_tx_tvalid	TVALID	in [0:0]
axis_eth_tx_tready	TREADY	out [0:0]
axis_eth_tx_tlast	TLAST	in [0:0]
axis_eth_tx_tuser	TUSER	in [16:0]

axis_eth_rx

Physical Port	Logical Port	Direction	Dependency
axis_eth_rx_tdata	TDATA	out [63:0]
axis_eth_rx_tkeep	TKEEP	out [7:0]
axis_eth_rx_tvalid	TVALID	out [0:0]
axis_eth_rx_tready	TREADY	in [0:0]
axis_eth_rx_tlast	TLAST	out [0:0]
axis_eth_rx_tuser	TUSER	out [0:0]

ctrl_reg

Physical Port	Logical Port	Direction	Dependency
ctrl_reg_wr_addr	ctrl_reg_wr_addr	in [18:0]
ctrl_reg_wr_data	ctrl_reg_wr_data	in [31:0]
ctrl_reg_wr_strb	ctrl_reg_wr_strb	in [3:0]
ctrl_reg_wr_en	ctrl_reg_wr_en	in
ctrl_reg_wr_wait	ctrl_reg_wr_wait	out
ctrl_reg_wr_ack	ctrl_reg_wr_ack	out
ctrl_reg_rd_addr	ctrl_reg_rd_addr	in [18:0]
ctrl_reg_rd_data	ctrl_reg_rd_data	out [31:0]
ctrl_reg_rd_en	ctrl_reg_rd_en	in
ctrl_reg_rd_wait	ctrl_reg_rd_wait	out
ctrl_reg_rd_ack	ctrl_reg_rd_ack	out

flow_control_tx

Physical Port	Logical Port	Direction	Dependency
eth_tx_enable	tx_enable	in [0:0]
eth_tx_status	tx_status	out [0:0]
eth_tx_lfc_en	tx_lfc_en	in [0:0]
eth_tx_lfc_req	tx_lfc_req	in [0:0]
eth_tx_pfc_en	tx_pfc_en	in [7:0]
eth_tx_pfc_req	tx_pfc_req	in [7:0]
eth_tx_fc_quanta_clk_en	tx_fc_quanta_clk_en	out [7:0]

flow_control_rx

Physical Port	Logical Port	Direction	Dependency
eth_rx_enable	rx_enable	in [0:0]
eth_rx_status	rx_status	out [0:0]
eth_rx_lfc_en	rx_lfc_en	in [0:0]
eth_rx_lfc_req	rx_lfc_req	out [0:0]
eth_rx_lfc_ack	rx_lfc_ack	in [0:0]
eth_rx_pfc_en	rx_pfc_en	in [7:0]
eth_rx_pfc_req	rx_pfc_req	out [7:0]
eth_rx_pfc_ack	rx_pfc_ack	in [7:0]
eth_rx_fc_quanta_clk_en	rx_fc_quanta_clk_en	out [0:0]

axis_tx_ptp

Physical Port	Logical Port	Direction	Dependency
axis_eth_tx_ptp_ts	ts	out [63:0]
axis_eth_tx_ptp_ts_tag	tag	out [15:0]
axis_eth_tx_ptp_ts_valid	valid	out [0:0]
axis_eth_tx_ptp_ts_ready	ready	in [0:0]

clk

Physical Port	Logical Port	Direction	Dependency
clk	CLK	in

rst

Physical Port	Logical Port	Direction	Dependency
rst	RST	in

ptp_clk

Physical Port	Logical Port	Direction	Dependency
ptp_clk	CLK	out

ptp_sample_clk

Physical Port	Logical Port	Direction	Dependency
ptp_sample_clk	CLK	out

eth_tx_clk

Physical Port	Logical Port	Direction	Dependency
eth_tx_clk	CLK	out [0:0]

eth_rx_clk

Physical Port	Logical Port	Direction	Dependency
eth_rx_clk	CLK	out [0:0]

ptp_rst

Physical Port	Logical Port	Direction	Dependency
ptp_rst	RST	out

eth_tx_rst

Physical Port	Logical Port	Direction	Dependency
eth_tx_rst	RST	out [0:0]

eth_rx_rst

Physical Port	Logical Port	Direction	Dependency
eth_rx_rst	RST	out [0:0]

ethernet_ptp_tx

Physical Port	Logical Port	Direction	Dependency
eth_tx_clk	ptp_clk	out [0:0]
eth_tx_rst	ptp_rst	out [0:0]
eth_tx_ptp_ts	ptp_ts	in [63:0]
eth_tx_ptp_ts_step	ptp_ts_step	in [0:0]

ethernet_ptp_rx

Physical Port	Logical Port	Direction	Dependency
eth_rx_clk	ptp_clk	out [0:0]
eth_rx_rst	ptp_rst	out [0:0]
eth_rx_ptp_ts	ptp_ts	in [63:0]
eth_rx_ptp_ts_step	ptp_ts_step	in [0:0]

m_axis_stat

Physical Port	Logical Port	Direction	Dependency
s_axis_stat_tdata	TDATA	out [23:0]
s_axis_stat_tid	TID	out [11:0]
s_axis_stat_tvalid	TVALID	out
s_axis_stat_tready	TREADY	in

m_sfp

Physical Port	Logical Port	Direction	Dependency
sfp_rx_p	rx_p	in
sfp_rx_n	rx_n	in
sfp_tx_p	tx_p	out
sfp_tx_n	tx_n	out
sfp_mgt_refclk_p	mgt_refclk_p	in
sfp_mgt_refclk_n	mgt_refclk_n	in

iic

Physical Port	Logical Port	Direction	Dependency
scl_i	SCL_I	in
scl_o	SCL_O	out
scl_t	SCL_T	out
sda_i	SDA_I	in
sda_o	SDA_O	out
sda_t	SDA_T	out

s_axil_csr

Enabled if PARAM_VALUE.AXIL_CSR_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axil_csr_awaddr	AWADDR	in [18:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_awprot	AWPROT	in [2:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_awvalid	AWVALID	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_awready	AWREADY	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_wdata	WDATA	in [31:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_wstrb	WSTRB	in [3:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_wvalid	WVALID	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_wready	WREADY	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_bresp	BRESP	out [1:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_bvalid	BVALID	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_bready	BREADY	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_araddr	ARADDR	in [18:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_arprot	ARPROT	in [2:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_arvalid	ARVALID	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_arready	ARREADY	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_rdata	RDATA	out [31:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_rresp	RRESP	out [1:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_rvalid	RVALID	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
s_axil_csr_rready	RREADY	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1

ptp_clock

Physical Port	Logical Port	Direction	Dependency
ptp_td_sd	ptp_td_sd	in
ptp_pps	ptp_pps	in
ptp_pps_str	ptp_pps_str	in
ptp_sync_locked	ptp_sync_locked	in
ptp_sync_ts_rel	ptp_sync_ts_rel	in [63:0]
ptp_sync_ts_rel_step	ptp_sync_ts_rel_step	in
ptp_sync_ts_tod	ptp_sync_ts_tod	in [96:0]
ptp_sync_ts_tod_step	ptp_sync_ts_tod_step	in
ptp_sync_pps	ptp_sync_pps	in
ptp_sync_pps_str	ptp_sync_pps_str	in
ptp_perout_locked	ptp_perout_locked	in [0:0]
ptp_perout_error	ptp_perout_error	in [0:0]
ptp_perout_pulse	ptp_perout_pulse	in [0:0]

Ports

Physical Port	Direction	Dependency	Description
led	out [1:0]
sfp_led	out [1:0]
sfp_tx_disable	out
sfp_tx_fault	in
sfp_rx_los	in
sfp_mod_abs	in

References

• HDL IP core at library/corundum/ethernet_core