Corundum Core

The Corundum Core is common in all projects and is used by the Corundum Network Stack. It repackages part of the Corundum NIC as an IP Core to be used with the ADI workflow.

Features

• Supports ARM and Microblaze processors

Files

Name	Description
library/corundum/corundum_core/corundum.v	Verilog source for the Corundum Core top module.
library/corundum/corundum_core/corundum_ip.tcl	TCL script to generate the Vivado IP-integrator project.
library/corundum/corundum_core/mqnic_app_block.v	Verilog source for the Application Core that is found inside the Corundum core.
library/corundum/corundum_core/mqnic_app_custom_params.vh	Verilog header file used to parameterize the Application Core.
library/corundum/corundum_core/mqnic_app_custom_ports.vh	Verilog header file used to create the ports and interfaces for the Application Core.

Configuration Parameters

Name	Description	Default Value	Choices/Range
FPGA_ID	Fpga Id.	'hDEADBEEF
FW_ID	Firmware ID.	'h00000000
FW_VER	Firmware version.	'h00000100
BOARD_ID	Board ID.	'h12340000
BOARD_VER	Board version.	'h01000000
BUILD_DATE	Build date.	'h23F0AF00
GIT_HASH	Git hash.	'hDCE357BF
RELEASE_INFO	Release info.	'h00000000
IF_COUNT	Interface count.	1
PORTS_PER_IF	Ports per interface.	1
SCHED_PER_IF	Schedulers per interface.	1
PORT_COUNT	Port count.	1
CLK_PERIOD_NS_NUM	Clock period nominator.	4
CLK_PERIOD_NS_DENOM	Clock period denominator.	1
PTP_CLK_PERIOD_NS_NUM	PTP clock period denominator.	4
PTP_CLK_PERIOD_NS_DENOM	PTP clock denominator.	1
PTP_CLOCK_PIPELINE	PTP clock pipeline.	0
PTP_CLOCK_CDC_PIPELINE	PTP clock CDC pipeline.	0
PTP_SEPARATE_TX_CLOCK	PTP separate TX clock.	0
PTP_SEPARATE_RX_CLOCK	PTP separate RX clock.	0
PTP_PORT_CDC_PIPELINE	PTP port CDC pipeline.	0
PTP_PEROUT_ENABLE	PTP perout enable.	0
PTP_PEROUT_COUNT	PTP perout count.	1
EVENT_QUEUE_OP_TABLE_SIZE	Event queue operation table size.	32
TX_QUEUE_OP_TABLE_SIZE	TX queue operation table size.	32
RX_QUEUE_OP_TABLE_SIZE	RX queue operation table size.	32
CQ_OP_TABLE_SIZE	Completion queue operation table size.	32
EQN_WIDTH	Event queue number width.	5
TX_QUEUE_INDEX_WIDTH	TX queue index width.	13
RX_QUEUE_INDEX_WIDTH	RX queue index width.	8
CQN_WIDTH	Completion queue number width.	14
EQ_PIPELINE	Event queue pipeline.	3
TX_QUEUE_PIPELINE	TX queue pipeline.	4
RX_QUEUE_PIPELINE	RX queue pipeline.	3
CQ_PIPELINE	Completion queue pipeline.	5
TX_DESC_TABLE_SIZE	TX descriptor table size.	32
RX_DESC_TABLE_SIZE	RX descriptor table size.	32
RX_INDIR_TBL_ADDR_WIDTH	RX indirect table address width.	8
TX_SCHEDULER_OP_TABLE_SIZE	TX scheduler operation table size.	32
TX_SCHEDULER_PIPELINE	TX scheduler pipeline.	4
TDMA_INDEX_WIDTH	TDMA index width.	6
PTP_TS_ENABLE	PTP TS enable.	1
PTP_TS_FMT_TOD	Ptp Ts Fmt Tod.	1
PTP_TS_WIDTH	PTP TS width.	64
TX_CPL_ENABLE	TX CPL enable.	1
TX_CPL_FIFO_DEPTH	TX CPL FIFO depth.	32
TX_TAG_WIDTH	TX tag width.	6
TX_CHECKSUM_ENABLE	TX checksum enable.	1
RX_HASH_ENABLE	RX hash enable.	1
RX_CHECKSUM_ENABLE	RX checksum enable.	1
PFC_ENABLE	PFC enable.	1
LFC_ENABLE	LFC enable.	1
MAC_CTRL_ENABLE	MAC control enable.	0
TX_FIFO_DEPTH	TX FIFO depth.	32768
RX_FIFO_DEPTH	RX FIFO depth.	32768
MAX_TX_SIZE	Max TX size.	9214
MAX_RX_SIZE	Max RX size.	9214
TX_RAM_SIZE	TX RAM size.	32768
RX_RAM_SIZE	RX RAM size.	32768
DDR_CH	DDR channels.	1
DDR_ENABLE	DDR enable.	0
DDR_GROUP_SIZE	DDR group size.	1
AXI_DDR_DATA_WIDTH	AXI DDR data width.	256
AXI_DDR_ADDR_WIDTH	AXI DDR address width.	32
AXI_DDR_STRB_WIDTH	AXI DDR strobe width.	32
AXI_DDR_ID_WIDTH	AXI DDR ID width.	8
AXI_DDR_AWUSER_ENABLE	AXI DDR awuser enable.	0
AXI_DDR_AWUSER_WIDTH	AXI DDR awuser width.	1
AXI_DDR_WUSER_ENABLE	AXI DDR wuser enable.	0
AXI_DDR_WUSER_WIDTH	AXI DDR wuser width.	1
AXI_DDR_BUSER_ENABLE	AXI DDR buser enable.	0
AXI_DDR_BUSER_WIDTH	AXI DDR buser width.	1
AXI_DDR_ARUSER_ENABLE	AXI DDR aruser enable.	0
AXI_DDR_ARUSER_WIDTH	AXI DDR aruser width.	1
AXI_DDR_RUSER_ENABLE	AXI DDR ruser enable.	0
AXI_DDR_RUSER_WIDTH	AXI DDR user width.	1
AXI_DDR_MAX_BURST_LEN	AXI DDR max burst length.	256
AXI_DDR_NARROW_BURST	AXI DDR narrow burst.	0
AXI_DDR_FIXED_BURST	AXI DDR fixed burst.	0
AXI_DDR_WRAP_BURST	AXI DDR wrap burst.	0
HBM_CH	HBM channels.	1
HBM_ENABLE	HBM enable.	0
HBM_GROUP_SIZE	HBM group size.	1
AXI_HBM_DATA_WIDTH	AXI HBM data width.	256
AXI_HBM_ADDR_WIDTH	AXI HBM address width.	32
AXI_HBM_STRB_WIDTH	AXI HBM strobe width.	32
AXI_HBM_ID_WIDTH	AXI HBM ID width.	8
AXI_HBM_AWUSER_ENABLE	AXI HBM awuser enable.	0
AXI_HBM_AWUSER_WIDTH	AXI HBM awuser width.	1
AXI_HBM_WUSER_ENABLE	AXI HBM wuser enable.	0
AXI_HBM_WUSER_WIDTH	AXI HBM wuser width.	1
AXI_HBM_BUSER_ENABLE	AXI HBM buser enable.	0
AXI_HBM_BUSER_WIDTH	AXI HBM buser width.	1
AXI_HBM_ARUSER_ENABLE	AXI HBM aruser enable.	0
AXI_HBM_ARUSER_WIDTH	AXI HBM aruser width.	1
AXI_HBM_RUSER_ENABLE	AXI HBM ruser enable.	0
AXI_HBM_RUSER_WIDTH	AXI HBM ruser width.	1
AXI_HBM_MAX_BURST_LEN	AXI HBM max burst length.	256
AXI_HBM_NARROW_BURST	AXI HBM narrow burst.	0
AXI_HBM_FIXED_BURST	AXI HBM fixed burst.	0
AXI_HBM_WRAP_BURST	AXI HBM wrap burst.	0
APP_ID	Application ID.	'h00000000
APP_ENABLE	Application enable.	0
APP_CTRL_ENABLE	Application control enable.	1
APP_DMA_ENABLE	Application DMA enable.	1
APP_AXIS_DIRECT_ENABLE	Application AXI4 Stream direct enable.	1
APP_AXIS_SYNC_ENABLE	Application AXI4 Stream sync enable.	1
APP_AXIS_IF_ENABLE	Application AXI4 Stream interface enable.	1
APP_STAT_ENABLE	Application statistics enable.	1
DMA_ADDR_WIDTH_APP	DMA address width.	0
RAM_SEL_WIDTH_APP	RAM select width.	0
RAM_SEG_COUNT_APP	RAM segment count.	0
RAM_SEG_DATA_WIDTH_APP	RAM segment data width.	0
RAM_SEG_BE_WIDTH_APP	RAM segment byte enable width.	0
RAM_SEG_ADDR_WIDTH_APP	RAM segment address width.	0
AXIS_SYNC_KEEP_WIDTH_APP	AXI4 Stream sync keep width.	0
AXIS_SYNC_TX_USER_WIDTH_APP	AXI4 Stream sync TX user width.	0
AXIS_SYNC_RX_USER_WIDTH_APP	AXI4 Stream sync RX user width.	0
AXIS_IF_KEEP_WIDTH_APP	AXI4 Stream interface keep width.	0
AXIS_IF_TX_ID_WIDTH_APP	AXI4 Stream interface TX ID width.	0
AXIS_IF_RX_ID_WIDTH_APP	AXI4 Stream interface RX ID width.	0
AXIS_IF_TX_DEST_WIDTH_APP	AXI4 Stream interface TX destination width.	0
AXIS_IF_RX_DEST_WIDTH_APP	AXI4 Stream interface RX destination width.	0
AXIS_IF_TX_USER_WIDTH_APP	AXI4 Stream interface TX user width.	0
AXIS_IF_RX_USER_WIDTH_APP	AXI4 Stream interface RX user width.	0
AXI_DATA_WIDTH	AXI data width.	128
AXI_ADDR_WIDTH	AXI address width.	64
AXI_STRB_WIDTH	AXI strobe width.	16
AXI_ID_WIDTH	AXI ID width.	8
DMA_IMM_ENABLE	DMA IMM enable.	0
DMA_IMM_WIDTH	DMA IMM width.	32
DMA_LEN_WIDTH	DMA length width.	16
DMA_TAG_WIDTH	DMA tag width.	16
RAM_ADDR_WIDTH	RAM address width.	15
RAM_PIPELINE	RAM pipeline.	2
AXI_DMA_MAX_BURST_LEN	AXI DMA Max burst length.	256
AXI_DMA_READ_USE_ID	AXI DMA read use ID.	0
AXI_DMA_WRITE_USE_ID	AXI DMA write use ID.	1
AXI_DMA_READ_OP_TABLE_SIZE	AXI DMA read operation table size.	256
AXI_DMA_WRITE_OP_TABLE_SIZE	AXI DMA write operation table size.	256
IRQ_COUNT	Interrupt request count.	32
AXIL_CTRL_DATA_WIDTH	AXI4 Lite control data width.	32
AXIL_CTRL_ADDR_WIDTH	AXI4 Lite control address width.	24
AXIL_CTRL_STRB_WIDTH	AXI4 Lite control strobe width.	4
AXIL_IF_CTRL_ADDR_WIDTH	AXI4 Lite interface control address width.	24
AXIL_CSR_ADDR_WIDTH	AXI4 Lite CSR address width.	19
AXIL_CSR_PASSTHROUGH_ENABLE	AXI4 Lite CSR passthrough enable.	0
RB_NEXT_PTR	Register base next pointer.	'h00000000
AXIL_APP_CTRL_DATA_WIDTH	AXI4 Lite application control data width.	32
AXIL_APP_CTRL_ADDR_WIDTH	AXI4 Lite application control address width.	24
AXIL_APP_CTRL_STRB_WIDTH	AXI4 Lite application control strobe width.	4
AXIS_DATA_WIDTH	AXI4 Stream data width.	64
AXIS_KEEP_WIDTH	AXI4 Stream keep width.	8
AXIS_SYNC_DATA_WIDTH	AXI4 Stream sync data width.	64
AXIS_IF_DATA_WIDTH	AXI4 Stream interface data width.	64
AXIS_TX_USER_WIDTH	AXI4 Stream TX user width.	7
AXIS_RX_USER_WIDTH	AXI4 Stream RX user width.	1
AXIS_RX_USE_READY	AXI4 Stream RX use ready.	0
AXIS_TX_PIPELINE	AXI4 Stream TX pipeline.	0
AXIS_TX_FIFO_PIPELINE	AXI4 Stream TX FIFO pipeline.	2
AXIS_TX_TS_PIPELINE	AXI4 Stream TX TS pipeline.	0
AXIS_RX_PIPELINE	AXI4 Stream RX pipeline.	0
AXIS_RX_FIFO_PIPELINE	AXI4 Stream RX FIFO pipeline.	2
STAT_ENABLE	Statistics enable.	1
STAT_DMA_ENABLE	Statistics DMA enable.	1
STAT_AXI_ENABLE	Statistics AXI enable.	1
STAT_INC_WIDTH	Statistics increment width.	24
STAT_ID_WIDTH	Statistics ID width.	12
AXIL_CSR_ENABLE	AXI4 Lite CSR enable.	0

Interface

m_axi

Physical Port	Logical Port	Direction	Dependency
m_axi_awid	AWID	out [7:0]
m_axi_awaddr	AWADDR	out [63:0]
m_axi_awlen	AWLEN	out [7:0]
m_axi_awsize	AWSIZE	out [2:0]
m_axi_awburst	AWBURST	out [1:0]
m_axi_awlock	AWLOCK	out
m_axi_awcache	AWCACHE	out [3:0]
m_axi_awprot	AWPROT	out [2:0]
m_axi_awvalid	AWVALID	out
m_axi_awready	AWREADY	in
m_axi_wdata	WDATA	out [127:0]
m_axi_wstrb	WSTRB	out [15:0]
m_axi_wlast	WLAST	out
m_axi_wvalid	WVALID	out
m_axi_wready	WREADY	in
m_axi_bid	BID	in [7:0]
m_axi_bresp	BRESP	in [1:0]
m_axi_bvalid	BVALID	in
m_axi_bready	BREADY	out
m_axi_arid	ARID	out [7:0]
m_axi_araddr	ARADDR	out [63:0]
m_axi_arlen	ARLEN	out [7:0]
m_axi_arsize	ARSIZE	out [2:0]
m_axi_arburst	ARBURST	out [1:0]
m_axi_arlock	ARLOCK	out
m_axi_arcache	ARCACHE	out [3:0]
m_axi_arprot	ARPROT	out [2:0]
m_axi_arvalid	ARVALID	out
m_axi_arready	ARREADY	in
m_axi_rid	RID	in [7:0]
m_axi_rdata	RDATA	in [127:0]
m_axi_rresp	RRESP	in [1:0]
m_axi_rlast	RLAST	in
m_axi_rvalid	RVALID	in
m_axi_rready	RREADY	out

s_axil_ctrl

Physical Port	Logical Port	Direction	Dependency
s_axil_ctrl_awaddr	AWADDR	in [23:0]
s_axil_ctrl_awprot	AWPROT	in [2:0]
s_axil_ctrl_awvalid	AWVALID	in
s_axil_ctrl_awready	AWREADY	out
s_axil_ctrl_wdata	WDATA	in [31:0]
s_axil_ctrl_wstrb	WSTRB	in [3:0]
s_axil_ctrl_wvalid	WVALID	in
s_axil_ctrl_wready	WREADY	out
s_axil_ctrl_bresp	BRESP	out [1:0]
s_axil_ctrl_bvalid	BVALID	out
s_axil_ctrl_bready	BREADY	in
s_axil_ctrl_araddr	ARADDR	in [23:0]
s_axil_ctrl_arprot	ARPROT	in [2:0]
s_axil_ctrl_arvalid	ARVALID	in
s_axil_ctrl_arready	ARREADY	out
s_axil_ctrl_rdata	RDATA	out [31:0]
s_axil_ctrl_rresp	RRESP	out [1:0]
s_axil_ctrl_rvalid	RVALID	out
s_axil_ctrl_rready	RREADY	in

m_axil_csr

Enabled if PARAM_VALUE.AXIL_CSR_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axil_csr_awaddr	AWADDR	out [18:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_awprot	AWPROT	out [2:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_awvalid	AWVALID	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_awready	AWREADY	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_wdata	WDATA	out [31:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_wstrb	WSTRB	out [3:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_wvalid	WVALID	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_wready	WREADY	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_bresp	BRESP	in [1:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_bvalid	BVALID	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_bready	BREADY	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_araddr	ARADDR	out [18:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_arprot	ARPROT	out [2:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_arvalid	ARVALID	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_arready	ARREADY	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_rdata	RDATA	in [31:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_rresp	RRESP	in [1:0]	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_rvalid	RVALID	in	PARAM_VALUE.AXIL_CSR_ENABLE = 1
m_axil_csr_rready	RREADY	out	PARAM_VALUE.AXIL_CSR_ENABLE = 1

m_axi_ddr

Enabled if DDR_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axi_ddr_awid	AWID	out [7:0]	DDR_ENABLE = 1
m_axi_ddr_awaddr	AWADDR	out [31:0]	DDR_ENABLE = 1
m_axi_ddr_awlen	AWLEN	out [7:0]	DDR_ENABLE = 1
m_axi_ddr_awsize	AWSIZE	out [2:0]	DDR_ENABLE = 1
m_axi_ddr_awuser	AWUSER	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_awburst	AWBURST	out [1:0]	DDR_ENABLE = 1
m_axi_ddr_awlock	AWLOCK	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_awcache	AWCACHE	out [3:0]	DDR_ENABLE = 1
m_axi_ddr_awprot	AWPROT	out [2:0]	DDR_ENABLE = 1
m_axi_ddr_awqos	AWQOS	out [3:0]	DDR_ENABLE = 1
m_axi_ddr_awvalid	AWVALID	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_awready	AWREADY	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_wdata	WDATA	out [255:0]	DDR_ENABLE = 1
m_axi_ddr_wstrb	WSTRB	out [31:0]	DDR_ENABLE = 1
m_axi_ddr_wlast	WLAST	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_wvalid	WVALID	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_wready	WREADY	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_wuser	WUSER	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_bid	BID	in [7:0]	DDR_ENABLE = 1
m_axi_ddr_bresp	BRESP	in [1:0]	DDR_ENABLE = 1
m_axi_ddr_buser	BUSER	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_bvalid	BVALID	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_bready	BREADY	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_arid	ARID	out [7:0]	DDR_ENABLE = 1
m_axi_ddr_araddr	ARADDR	out [31:0]	DDR_ENABLE = 1
m_axi_ddr_arlen	ARLEN	out [7:0]	DDR_ENABLE = 1
m_axi_ddr_arsize	ARSIZE	out [2:0]	DDR_ENABLE = 1
m_axi_ddr_aruser	ARUSER	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_arburst	ARBURST	out [1:0]	DDR_ENABLE = 1
m_axi_ddr_arlock	ARLOCK	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_arcache	ARCACHE	out [3:0]	DDR_ENABLE = 1
m_axi_ddr_arprot	ARPROT	out [2:0]	DDR_ENABLE = 1
m_axi_ddr_arqos	ARQOS	out [3:0]	DDR_ENABLE = 1
m_axi_ddr_arvalid	ARVALID	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_arready	ARREADY	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_rid	RID	in [7:0]	DDR_ENABLE = 1
m_axi_ddr_rdata	RDATA	in [255:0]	DDR_ENABLE = 1
m_axi_ddr_rresp	RRESP	in [1:0]	DDR_ENABLE = 1
m_axi_ddr_ruser	RUSER	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_rlast	RLAST	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_rvalid	RVALID	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_rready	RREADY	out [0:0]	DDR_ENABLE = 1

m_axi_hbm

Enabled if HBM_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axi_hbm_awid	AWID	out [7:0]	HBM_ENABLE = 1
m_axi_hbm_awaddr	AWADDR	out [31:0]	HBM_ENABLE = 1
m_axi_hbm_awlen	AWLEN	out [7:0]	HBM_ENABLE = 1
m_axi_hbm_awsize	AWSIZE	out [2:0]	HBM_ENABLE = 1
m_axi_hbm_awuser	AWUSER	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_awburst	AWBURST	out [1:0]	HBM_ENABLE = 1
m_axi_hbm_awlock	AWLOCK	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_awcache	AWCACHE	out [3:0]	HBM_ENABLE = 1
m_axi_hbm_awprot	AWPROT	out [2:0]	HBM_ENABLE = 1
m_axi_hbm_awqos	AWQOS	out [3:0]	HBM_ENABLE = 1
m_axi_hbm_awvalid	AWVALID	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_awready	AWREADY	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_wdata	WDATA	out [255:0]	HBM_ENABLE = 1
m_axi_hbm_wstrb	WSTRB	out [31:0]	HBM_ENABLE = 1
m_axi_hbm_wlast	WLAST	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_wvalid	WVALID	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_wready	WREADY	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_wuser	WUSER	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_bid	BID	in [7:0]	HBM_ENABLE = 1
m_axi_hbm_bresp	BRESP	in [1:0]	HBM_ENABLE = 1
m_axi_hbm_buser	BUSER	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_bvalid	BVALID	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_bready	BREADY	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_arid	ARID	out [7:0]	HBM_ENABLE = 1
m_axi_hbm_araddr	ARADDR	out [31:0]	HBM_ENABLE = 1
m_axi_hbm_arlen	ARLEN	out [7:0]	HBM_ENABLE = 1
m_axi_hbm_arsize	ARSIZE	out [2:0]	HBM_ENABLE = 1
m_axi_hbm_aruser	ARUSER	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_arburst	ARBURST	out [1:0]	HBM_ENABLE = 1
m_axi_hbm_arlock	ARLOCK	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_arcache	ARCACHE	out [3:0]	HBM_ENABLE = 1
m_axi_hbm_arprot	ARPROT	out [2:0]	HBM_ENABLE = 1
m_axi_hbm_arqos	ARQOS	out [3:0]	HBM_ENABLE = 1
m_axi_hbm_arvalid	ARVALID	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_arready	ARREADY	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_rid	RID	in [7:0]	HBM_ENABLE = 1
m_axi_hbm_rdata	RDATA	in [255:0]	HBM_ENABLE = 1
m_axi_hbm_rresp	RRESP	in [1:0]	HBM_ENABLE = 1
m_axi_hbm_ruser	RUSER	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_rlast	RLAST	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_rvalid	RVALID	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_rready	RREADY	out [0:0]	HBM_ENABLE = 1

m_axis_tx

Physical Port	Logical Port	Direction	Dependency
m_axis_tx_tdata	TDATA	out [63:0]
m_axis_tx_tkeep	TKEEP	out [7:0]
m_axis_tx_tvalid	TVALID	out [0:0]
m_axis_tx_tready	TREADY	in [0:0]
m_axis_tx_tlast	TLAST	out [0:0]
m_axis_tx_tuser	TUSER	out [6:0]

s_axis_rx

Physical Port	Logical Port	Direction	Dependency
s_axis_rx_tdata	TDATA	in [63:0]
s_axis_rx_tkeep	TKEEP	in [7:0]
s_axis_rx_tvalid	TVALID	in [0:0]
s_axis_rx_tready	TREADY	out [0:0]
s_axis_rx_tlast	TLAST	in [0:0]
s_axis_rx_tuser	TUSER	in [0:0]

s_axis_stat

Physical Port	Logical Port	Direction	Dependency
s_axis_stat_tdata	TDATA	in [23:0]
s_axis_stat_tid	TID	in [11:0]
s_axis_stat_tvalid	TVALID	in
s_axis_stat_tready	TREADY	out

ctrl_reg

Physical Port	Logical Port	Direction	Dependency
ctrl_reg_wr_addr	ctrl_reg_wr_addr	out [18:0]
ctrl_reg_wr_data	ctrl_reg_wr_data	out [31:0]
ctrl_reg_wr_strb	ctrl_reg_wr_strb	out [3:0]
ctrl_reg_wr_en	ctrl_reg_wr_en	out
ctrl_reg_wr_wait	ctrl_reg_wr_wait	in
ctrl_reg_wr_ack	ctrl_reg_wr_ack	in
ctrl_reg_rd_addr	ctrl_reg_rd_addr	out [18:0]
ctrl_reg_rd_data	ctrl_reg_rd_data	in [31:0]
ctrl_reg_rd_en	ctrl_reg_rd_en	out
ctrl_reg_rd_wait	ctrl_reg_rd_wait	in
ctrl_reg_rd_ack	ctrl_reg_rd_ack	in

ptp_clock

Physical Port	Logical Port	Direction	Dependency
ptp_td_sd	ptp_td_sd	out
ptp_pps	ptp_pps	out
ptp_pps_str	ptp_pps_str	out
ptp_sync_locked	ptp_sync_locked	out
ptp_sync_ts_rel	ptp_sync_ts_rel	out [63:0]
ptp_sync_ts_rel_step	ptp_sync_ts_rel_step	out
ptp_sync_ts_tod	ptp_sync_ts_tod	out [96:0]
ptp_sync_ts_tod_step	ptp_sync_ts_tod_step	out
ptp_sync_pps	ptp_sync_pps	out
ptp_sync_pps_str	ptp_sync_pps_str	out
ptp_perout_locked	ptp_perout_locked	out [0:0]
ptp_perout_error	ptp_perout_error	out [0:0]
ptp_perout_pulse	ptp_perout_pulse	out [0:0]

flow_control_tx

Physical Port	Logical Port	Direction	Dependency
tx_enable	tx_enable	out [0:0]
tx_status	tx_status	in [0:0]
tx_lfc_en	tx_lfc_en	out [0:0]
tx_lfc_req	tx_lfc_req	out [0:0]
tx_pfc_en	tx_pfc_en	out [7:0]
tx_pfc_req	tx_pfc_req	out [7:0]
tx_fc_quanta_clk_en	tx_fc_quanta_clk_en	in [0:0]

flow_control_rx

Physical Port	Logical Port	Direction	Dependency
rx_enable	rx_enable	out [0:0]
rx_status	rx_status	in [0:0]
rx_lfc_en	rx_lfc_en	out [0:0]
rx_lfc_req	rx_lfc_req	in [0:0]
rx_lfc_ack	rx_lfc_ack	out [0:0]
rx_pfc_en	rx_pfc_en	out [7:0]
rx_pfc_req	rx_pfc_req	in [7:0]
rx_pfc_ack	rx_pfc_ack	out [7:0]
rx_fc_quanta_clk_en	rx_fc_quanta_clk_en	in [0:0]

ethernet_ptp_tx

Physical Port	Logical Port	Direction	Dependency
tx_ptp_clk	ptp_clk	in [0:0]
tx_ptp_rst	ptp_rst	in [0:0]
tx_ptp_ts	ptp_ts	out [63:0]
tx_ptp_ts_step	ptp_ts_step	out [0:0]

ethernet_ptp_rx

Physical Port	Logical Port	Direction	Dependency
rx_ptp_clk	ptp_clk	in [0:0]
rx_ptp_rst	ptp_rst	in [0:0]
rx_ptp_ts	ptp_ts	out [63:0]
rx_ptp_ts_step	ptp_ts_step	out [0:0]

axis_tx_ptp

Physical Port	Logical Port	Direction	Dependency
s_axis_tx_cpl_ts	ts	in [63:0]
s_axis_tx_cpl_tag	tag	in [5:0]
s_axis_tx_cpl_valid	valid	in [0:0]
s_axis_tx_cpl_ready	ready	out [0:0]

m_axi_ddr_app

Enabled if APP_ENABLE = 1 and  DDR_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axi_ddr_awid_app	AWID	in [7:0]	DDR_ENABLE = 1
m_axi_ddr_awaddr_app	AWADDR	in [31:0]	DDR_ENABLE = 1
m_axi_ddr_awlen_app	AWLEN	in [7:0]	DDR_ENABLE = 1
m_axi_ddr_awsize_app	AWSIZE	in [2:0]	DDR_ENABLE = 1
m_axi_ddr_awuser_app	AWUSER	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_awburst_app	AWBURST	in [1:0]	DDR_ENABLE = 1
m_axi_ddr_awlock_app	AWLOCK	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_awcache_app	AWCACHE	in [3:0]	DDR_ENABLE = 1
m_axi_ddr_awprot_app	AWPROT	in [2:0]	DDR_ENABLE = 1
m_axi_ddr_awqos_app	AWQOS	in [3:0]	DDR_ENABLE = 1
m_axi_ddr_awvalid_app	AWVALID	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_awready_app	AWREADY	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_wdata_app	WDATA	in [255:0]	DDR_ENABLE = 1
m_axi_ddr_wstrb_app	WSTRB	in [31:0]	DDR_ENABLE = 1
m_axi_ddr_wlast_app	WLAST	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_wvalid_app	WVALID	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_wready_app	WREADY	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_wuser_app	WUSER	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_bid_app	BID	out [7:0]	DDR_ENABLE = 1
m_axi_ddr_bresp_app	BRESP	out [1:0]	DDR_ENABLE = 1
m_axi_ddr_buser_app	BUSER	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_bvalid_app	BVALID	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_bready_app	BREADY	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_arid_app	ARID	in [7:0]	DDR_ENABLE = 1
m_axi_ddr_araddr_app	ARADDR	in [31:0]	DDR_ENABLE = 1
m_axi_ddr_arlen_app	ARLEN	in [7:0]	DDR_ENABLE = 1
m_axi_ddr_arsize_app	ARSIZE	in [2:0]	DDR_ENABLE = 1
m_axi_ddr_aruser_app	ARUSER	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_arburst_app	ARBURST	in [1:0]	DDR_ENABLE = 1
m_axi_ddr_arlock_app	ARLOCK	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_arcache_app	ARCACHE	in [3:0]	DDR_ENABLE = 1
m_axi_ddr_arprot_app	ARPROT	in [2:0]	DDR_ENABLE = 1
m_axi_ddr_arqos_app	ARQOS	in [3:0]	DDR_ENABLE = 1
m_axi_ddr_arvalid_app	ARVALID	in [0:0]	DDR_ENABLE = 1
m_axi_ddr_arready_app	ARREADY	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_rid_app	RID	out [7:0]	DDR_ENABLE = 1
m_axi_ddr_rdata_app	RDATA	out [255:0]	DDR_ENABLE = 1
m_axi_ddr_rresp_app	RRESP	out [1:0]	DDR_ENABLE = 1
m_axi_ddr_ruser_app	RUSER	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_rlast_app	RLAST	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_rvalid_app	RVALID	out [0:0]	DDR_ENABLE = 1
m_axi_ddr_rready_app	RREADY	in [0:0]	DDR_ENABLE = 1

m_axi_hbm_app

Enabled if APP_ENABLE = 1 and  HBM_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axi_hbm_awid_app	AWID	in [7:0]	HBM_ENABLE = 1
m_axi_hbm_awaddr_app	AWADDR	in [31:0]	HBM_ENABLE = 1
m_axi_hbm_awlen_app	AWLEN	in [7:0]	HBM_ENABLE = 1
m_axi_hbm_awsize_app	AWSIZE	in [2:0]	HBM_ENABLE = 1
m_axi_hbm_awuser_app	AWUSER	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_awburst_app	AWBURST	in [1:0]	HBM_ENABLE = 1
m_axi_hbm_awlock_app	AWLOCK	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_awcache_app	AWCACHE	in [3:0]	HBM_ENABLE = 1
m_axi_hbm_awprot_app	AWPROT	in [2:0]	HBM_ENABLE = 1
m_axi_hbm_awqos_app	AWQOS	in [3:0]	HBM_ENABLE = 1
m_axi_hbm_awvalid_app	AWVALID	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_awready_app	AWREADY	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_wdata_app	WDATA	in [255:0]	HBM_ENABLE = 1
m_axi_hbm_wstrb_app	WSTRB	in [31:0]	HBM_ENABLE = 1
m_axi_hbm_wlast_app	WLAST	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_wvalid_app	WVALID	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_wready_app	WREADY	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_wuser_app	WUSER	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_bid_app	BID	out [7:0]	HBM_ENABLE = 1
m_axi_hbm_bresp_app	BRESP	out [1:0]	HBM_ENABLE = 1
m_axi_hbm_buser_app	BUSER	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_bvalid_app	BVALID	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_bready_app	BREADY	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_arid_app	ARID	in [7:0]	HBM_ENABLE = 1
m_axi_hbm_araddr_app	ARADDR	in [31:0]	HBM_ENABLE = 1
m_axi_hbm_arlen_app	ARLEN	in [7:0]	HBM_ENABLE = 1
m_axi_hbm_arsize_app	ARSIZE	in [2:0]	HBM_ENABLE = 1
m_axi_hbm_aruser_app	ARUSER	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_arburst_app	ARBURST	in [1:0]	HBM_ENABLE = 1
m_axi_hbm_arlock_app	ARLOCK	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_arcache_app	ARCACHE	in [3:0]	HBM_ENABLE = 1
m_axi_hbm_arprot_app	ARPROT	in [2:0]	HBM_ENABLE = 1
m_axi_hbm_arqos_app	ARQOS	in [3:0]	HBM_ENABLE = 1
m_axi_hbm_arvalid_app	ARVALID	in [0:0]	HBM_ENABLE = 1
m_axi_hbm_arready_app	ARREADY	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_rid_app	RID	out [7:0]	HBM_ENABLE = 1
m_axi_hbm_rdata_app	RDATA	out [255:0]	HBM_ENABLE = 1
m_axi_hbm_rresp_app	RRESP	out [1:0]	HBM_ENABLE = 1
m_axi_hbm_ruser_app	RUSER	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_rlast_app	RLAST	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_rvalid_app	RVALID	out [0:0]	HBM_ENABLE = 1
m_axi_hbm_rready_app	RREADY	in [0:0]	HBM_ENABLE = 1

s_axis_direct_tx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_DIRECT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_direct_tx_tdata_app	TDATA	out [63:0]
s_axis_direct_tx_tkeep_app	TKEEP	out [7:0]
s_axis_direct_tx_tvalid_app	TVALID	out [0:0]
s_axis_direct_tx_tready_app	TREADY	in [0:0]
s_axis_direct_tx_tlast_app	TLAST	out [0:0]
s_axis_direct_tx_tuser_app	TUSER	out [6:0]

m_axis_direct_tx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_DIRECT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_direct_tx_tdata_app	TDATA	in [63:0]
m_axis_direct_tx_tkeep_app	TKEEP	in [7:0]
m_axis_direct_tx_tvalid_app	TVALID	in [0:0]
m_axis_direct_tx_tready_app	TREADY	out [0:0]
m_axis_direct_tx_tlast_app	TLAST	in [0:0]
m_axis_direct_tx_tuser_app	TUSER	in [6:0]

s_axis_direct_rx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_DIRECT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_direct_rx_tdata_app	TDATA	out [63:0]
s_axis_direct_rx_tkeep_app	TKEEP	out [7:0]
s_axis_direct_rx_tvalid_app	TVALID	out [0:0]
s_axis_direct_rx_tready_app	TREADY	in [0:0]
s_axis_direct_rx_tlast_app	TLAST	out [0:0]
s_axis_direct_rx_tuser_app	TUSER	out [0:0]

m_axis_direct_rx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_DIRECT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_direct_rx_tdata_app	TDATA	in [63:0]
m_axis_direct_rx_tkeep_app	TKEEP	in [7:0]
m_axis_direct_rx_tvalid_app	TVALID	in [0:0]
m_axis_direct_rx_tready_app	TREADY	out [0:0]
m_axis_direct_rx_tlast_app	TLAST	in [0:0]
m_axis_direct_rx_tuser_app	TUSER	in [0:0]

s_axis_sync_tx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_SYNC_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_sync_tx_tdata_app	TDATA	out [63:0]
s_axis_sync_tx_tkeep_app	TKEEP	out [0:0]
s_axis_sync_tx_tvalid_app	TVALID	out [0:0]
s_axis_sync_tx_tready_app	TREADY	in [0:0]
s_axis_sync_tx_tlast_app	TLAST	out [0:0]
s_axis_sync_tx_tuser_app	TUSER	out [0:0]

m_axis_sync_tx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_SYNC_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_sync_tx_tdata_app	TDATA	in [63:0]
m_axis_sync_tx_tkeep_app	TKEEP	in [0:0]
m_axis_sync_tx_tvalid_app	TVALID	in [0:0]
m_axis_sync_tx_tready_app	TREADY	out [0:0]
m_axis_sync_tx_tlast_app	TLAST	in [0:0]
m_axis_sync_tx_tuser_app	TUSER	in [0:0]

s_axis_sync_rx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_SYNC_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_sync_rx_tdata_app	TDATA	out [63:0]
s_axis_sync_rx_tkeep_app	TKEEP	out [0:0]
s_axis_sync_rx_tvalid_app	TVALID	out [0:0]
s_axis_sync_rx_tready_app	TREADY	in [0:0]
s_axis_sync_rx_tlast_app	TLAST	out [0:0]
s_axis_sync_rx_tuser_app	TUSER	out [0:0]

m_axis_sync_rx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_SYNC_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_sync_rx_tdata_app	TDATA	in [63:0]
m_axis_sync_rx_tkeep_app	TKEEP	in [0:0]
m_axis_sync_rx_tvalid_app	TVALID	in [0:0]
m_axis_sync_rx_tready_app	TREADY	out [0:0]
m_axis_sync_rx_tlast_app	TLAST	in [0:0]
m_axis_sync_rx_tuser_app	TUSER	in [0:0]

s_axis_if_tx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_IF_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_if_tx_tdata_app	TDATA	out [63:0]
s_axis_if_tx_tkeep_app	TKEEP	out [0:0]
s_axis_if_tx_tvalid_app	TVALID	out [0:0]
s_axis_if_tx_tready_app	TREADY	in [0:0]
s_axis_if_tx_tlast_app	TLAST	out [0:0]
s_axis_if_tx_tid_app	TID	out [0:0]
s_axis_if_tx_tdest_app	TDEST	out [0:0]
s_axis_if_tx_tuser_app	TUSER	out [0:0]

m_axis_if_tx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_IF_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_if_tx_tdata_app	TDATA	in [63:0]
m_axis_if_tx_tkeep_app	TKEEP	in [0:0]
m_axis_if_tx_tvalid_app	TVALID	in [0:0]
m_axis_if_tx_tready_app	TREADY	out [0:0]
m_axis_if_tx_tlast_app	TLAST	in [0:0]
m_axis_if_tx_tid_app	TID	in [0:0]
m_axis_if_tx_tdest_app	TDEST	in [0:0]
m_axis_if_tx_tuser_app	TUSER	in [0:0]

s_axis_if_rx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_IF_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_if_rx_tdata_app	TDATA	out [63:0]
s_axis_if_rx_tkeep_app	TKEEP	out [0:0]
s_axis_if_rx_tvalid_app	TVALID	out [0:0]
s_axis_if_rx_tready_app	TREADY	in [0:0]
s_axis_if_rx_tlast_app	TLAST	out [0:0]
s_axis_if_rx_tid_app	TID	out [0:0]
s_axis_if_rx_tdest_app	TDEST	out [0:0]
s_axis_if_rx_tuser_app	TUSER	out [0:0]

m_axis_if_rx_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_IF_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_if_rx_tdata_app	TDATA	in [63:0]
m_axis_if_rx_tkeep_app	TKEEP	in [0:0]
m_axis_if_rx_tvalid_app	TVALID	in [0:0]
m_axis_if_rx_tready_app	TREADY	out [0:0]
m_axis_if_rx_tlast_app	TLAST	in [0:0]
m_axis_if_rx_tid_app	TID	in [0:0]
m_axis_if_rx_tdest_app	TDEST	in [0:0]
m_axis_if_rx_tuser_app	TUSER	in [0:0]

s_axis_direct_tx_cpl_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_DIRECT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_direct_tx_cpl_ts_app	ts	out [63:0]
s_axis_direct_tx_cpl_tag_app	tag	out [5:0]
s_axis_direct_tx_cpl_valid_app	valid	out [0:0]
s_axis_direct_tx_cpl_ready_app	ready	in [0:0]

m_axis_direct_tx_cpl_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_DIRECT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_direct_tx_cpl_ts_app	ts	in [63:0]
m_axis_direct_tx_cpl_tag_app	tag	in [5:0]
m_axis_direct_tx_cpl_valid_app	valid	in [0:0]
m_axis_direct_tx_cpl_ready_app	ready	out [0:0]

s_axis_sync_tx_cpl_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_SYNC_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_sync_tx_cpl_ts_app	ts	out [63:0]
s_axis_sync_tx_cpl_tag_app	tag	out [5:0]
s_axis_sync_tx_cpl_valid_app	valid	out [0:0]
s_axis_sync_tx_cpl_ready_app	ready	in [0:0]

m_axis_sync_tx_cpl_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_SYNC_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_sync_tx_cpl_ts_app	ts	in [63:0]
m_axis_sync_tx_cpl_tag_app	tag	in [5:0]
m_axis_sync_tx_cpl_valid_app	valid	in [0:0]
m_axis_sync_tx_cpl_ready_app	ready	out [0:0]

s_axis_if_tx_cpl_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_IF_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_if_tx_cpl_ts_app	ts	out [63:0]
s_axis_if_tx_cpl_tag_app	tag	out [5:0]
s_axis_if_tx_cpl_valid_app	valid	out [0:0]
s_axis_if_tx_cpl_ready_app	ready	in [0:0]

m_axis_if_tx_cpl_app

Enabled if APP_ENABLE = 1 and  APP_AXIS_IF_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_if_tx_cpl_ts_app	ts	in [63:0]
m_axis_if_tx_cpl_tag_app	tag	in [5:0]
m_axis_if_tx_cpl_valid_app	valid	in [0:0]
m_axis_if_tx_cpl_ready_app	ready	out [0:0]

ptp_clock_app

Enabled if APP_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
ptp_td_sd_app	ptp_td_sd	out
ptp_pps_app	ptp_pps	out
ptp_pps_str_app	ptp_pps_str	out
ptp_sync_locked_app	ptp_sync_locked	out
ptp_sync_ts_rel_app	ptp_sync_ts_rel	out [63:0]
ptp_sync_ts_rel_step_app	ptp_sync_ts_rel_step	out
ptp_sync_ts_tod_app	ptp_sync_ts_tod	out [63:0]
ptp_sync_ts_tod_step_app	ptp_sync_ts_tod_step	out
ptp_sync_pps_app	ptp_sync_pps	out
ptp_sync_pps_str_app	ptp_sync_pps_str	out
ptp_perout_locked_app	ptp_perout_locked	out [0:0]
ptp_perout_error_app	ptp_perout_error	out [0:0]
ptp_perout_pulse_app	ptp_perout_pulse	out [0:0]

m_axil_ctrl_app

Enabled if APP_ENABLE = 1 and  APP_CTRL_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axil_ctrl_awaddr_app	AWADDR	in [23:0]
m_axil_ctrl_awprot_app	AWPROT	in [2:0]
m_axil_ctrl_awvalid_app	AWVALID	in
m_axil_ctrl_awready_app	AWREADY	out
m_axil_ctrl_wdata_app	WDATA	in [31:0]
m_axil_ctrl_wstrb_app	WSTRB	in [3:0]
m_axil_ctrl_wvalid_app	WVALID	in
m_axil_ctrl_wready_app	WREADY	out
m_axil_ctrl_bresp_app	BRESP	out [1:0]
m_axil_ctrl_bvalid_app	BVALID	out
m_axil_ctrl_bready_app	BREADY	in
m_axil_ctrl_araddr_app	ARADDR	in [23:0]
m_axil_ctrl_arprot_app	ARPROT	in [2:0]
m_axil_ctrl_arvalid_app	ARVALID	in
m_axil_ctrl_arready_app	ARREADY	out
m_axil_ctrl_rdata_app	RDATA	out [31:0]
m_axil_ctrl_rresp_app	RRESP	out [1:0]
m_axil_ctrl_rvalid_app	RVALID	out
m_axil_ctrl_rready_app	RREADY	in

m_axis_ctrl_dma_read_desc_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_ctrl_dma_read_desc_dma_addr_app	dma_addr	in [0:0]
m_axis_ctrl_dma_read_desc_ram_sel_app	ram_sel	in [0:0]
m_axis_ctrl_dma_read_desc_ram_addr_app	ram_addr	in [14:0]
m_axis_ctrl_dma_read_desc_len_app	len	in [15:0]
m_axis_ctrl_dma_read_desc_tag_app	tag	in [15:0]
m_axis_ctrl_dma_read_desc_valid_app	valid	in
m_axis_ctrl_dma_read_desc_ready_app	ready	out

m_axis_ctrl_dma_write_desc_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_ctrl_dma_write_desc_dma_addr_app	dma_addr	in [0:0]
m_axis_ctrl_dma_write_desc_ram_sel_app	ram_sel	in [0:0]
m_axis_ctrl_dma_write_desc_ram_addr_app	ram_addr	in [14:0]
m_axis_ctrl_dma_write_desc_imm_app	imm	in [31:0]
m_axis_ctrl_dma_write_desc_imm_en_app	imm_en	in
m_axis_ctrl_dma_write_desc_len_app	len	in [15:0]
m_axis_ctrl_dma_write_desc_tag_app	tag	in [15:0]
m_axis_ctrl_dma_write_desc_valid_app	valid	in
m_axis_ctrl_dma_write_desc_ready_app	ready	out

m_axis_data_dma_read_desc_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_data_dma_read_desc_dma_addr_app	dma_addr	in [0:0]
m_axis_data_dma_read_desc_ram_sel_app	ram_sel	in [0:0]
m_axis_data_dma_read_desc_ram_addr_app	ram_addr	in [14:0]
m_axis_data_dma_read_desc_len_app	len	in [15:0]
m_axis_data_dma_read_desc_tag_app	tag	in [15:0]
m_axis_data_dma_read_desc_valid_app	valid	in
m_axis_data_dma_read_desc_ready_app	ready	out

m_axis_data_dma_write_desc_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_data_dma_write_desc_dma_addr_app	dma_addr	in [0:0]
m_axis_data_dma_write_desc_ram_sel_app	ram_sel	in [0:0]
m_axis_data_dma_write_desc_ram_addr_app	ram_addr	in [14:0]
m_axis_data_dma_write_desc_imm_app	imm	in [31:0]
m_axis_data_dma_write_desc_imm_en_app	imm_en	in
m_axis_data_dma_write_desc_len_app	len	in [15:0]
m_axis_data_dma_write_desc_tag_app	tag	in [15:0]
m_axis_data_dma_write_desc_valid_app	valid	in
m_axis_data_dma_write_desc_ready_app	ready	out

s_axis_ctrl_dma_read_desc_status_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_ctrl_dma_read_desc_status_tag_app	tag	out [15:0]
s_axis_ctrl_dma_read_desc_status_error_app	error	out [3:0]
s_axis_ctrl_dma_read_desc_status_valid_app	valid	out

s_axis_ctrl_dma_write_desc_status_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_ctrl_dma_write_desc_status_tag_app	tag	out [15:0]
s_axis_ctrl_dma_write_desc_status_error_app	error	out [3:0]
s_axis_ctrl_dma_write_desc_status_valid_app	valid	out

s_axis_data_dma_read_desc_status_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_data_dma_read_desc_status_tag_app	tag	out [15:0]
s_axis_data_dma_read_desc_status_error_app	error	out [3:0]
s_axis_data_dma_read_desc_status_valid_app	valid	out

s_axis_data_dma_write_desc_status_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
s_axis_data_dma_write_desc_status_tag_app	tag	out [15:0]
s_axis_data_dma_write_desc_status_error_app	error	out [3:0]
s_axis_data_dma_write_desc_status_valid_app	valid	out

ctrl_dma_ram_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
ctrl_dma_ram_wr_cmd_sel_app	wr_cmd_sel	out [0:0]
ctrl_dma_ram_wr_cmd_be_app	wr_cmd_be	out [0:0]
ctrl_dma_ram_wr_cmd_addr_app	wr_cmd_addr	out [0:0]
ctrl_dma_ram_wr_cmd_data_app	wr_cmd_data	out [0:0]
ctrl_dma_ram_wr_cmd_valid_app	wr_cmd_valid	out [0:0]
ctrl_dma_ram_wr_cmd_ready_app	wr_cmd_ready	in [0:0]
ctrl_dma_ram_wr_done_app	wr_done	in [0:0]
ctrl_dma_ram_rd_cmd_sel_app	rd_cmd_sel	out [0:0]
ctrl_dma_ram_rd_cmd_addr_app	rd_cmd_addr	out [0:0]
ctrl_dma_ram_rd_cmd_valid_app	rd_cmd_valid	out [0:0]
ctrl_dma_ram_rd_cmd_ready_app	rd_cmd_ready	in [0:0]
ctrl_dma_ram_rd_resp_data_app	rd_resp_data	in [0:0]
ctrl_dma_ram_rd_resp_valid_app	rd_resp_valid	in [0:0]
ctrl_dma_ram_rd_resp_ready_app	rd_resp_ready	out [0:0]

data_dma_ram_app

Enabled if APP_ENABLE = 1 and  APP_DMA_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
data_dma_ram_wr_cmd_sel_app	wr_cmd_sel	out [0:0]
data_dma_ram_wr_cmd_be_app	wr_cmd_be	out [0:0]
data_dma_ram_wr_cmd_addr_app	wr_cmd_addr	out [0:0]
data_dma_ram_wr_cmd_data_app	wr_cmd_data	out [0:0]
data_dma_ram_wr_cmd_valid_app	wr_cmd_valid	out [0:0]
data_dma_ram_wr_cmd_ready_app	wr_cmd_ready	in [0:0]
data_dma_ram_wr_done_app	wr_done	in [0:0]
data_dma_ram_rd_cmd_sel_app	rd_cmd_sel	out [0:0]
data_dma_ram_rd_cmd_addr_app	rd_cmd_addr	out [0:0]
data_dma_ram_rd_cmd_valid_app	rd_cmd_valid	out [0:0]
data_dma_ram_rd_cmd_ready_app	rd_cmd_ready	in [0:0]
data_dma_ram_rd_resp_data_app	rd_resp_data	in [0:0]
data_dma_ram_rd_resp_valid_app	rd_resp_valid	in [0:0]
data_dma_ram_rd_resp_ready_app	rd_resp_ready	out [0:0]

m_axis_stat_app

Enabled if APP_ENABLE = 1 and  APP_STAT_ENABLE = 1.

Physical Port	Logical Port	Direction	Dependency
m_axis_stat_tdata_app	tdata	in [23:0]
m_axis_stat_tid_app	tid	in [11:0]
m_axis_stat_tvalid_app	tvalid	in
m_axis_stat_tready_app	tready	out

Ports

Physical Port	Direction	Dependency	Description
clk	in		Bus m_axi_s_axil_ctrl_m_axil_csr_s_axis_sync_tx_app_m_axis_sync_tx_app_s_axis_sync_rx_app_m_axis_sync_rx_app_s_axis_if_tx_app_m_axis_if_tx_app_s_axis_if_rx_app_m_axis_if_rx_app_m_axil_ctrl_app is synchronous to this clock domain.
rst	in		Bus m_axi_s_axil_ctrl_m_axil_csr_s_axis_sync_tx_app_m_axis_sync_tx_app_s_axis_sync_rx_app_m_axis_sync_rx_app_s_axis_if_tx_app_m_axis_if_tx_app_s_axis_if_rx_app_m_axis_if_rx_app_m_axil_ctrl_app is synchronous to this reset signal.
irq	out
ptp_clk	in
ptp_rst	in
ptp_sample_clk	in
tx_clk	in [0:0]		Bus m_axis_tx_s_axis_direct_tx_app_m_axis_direct_tx_app is synchronous to this clock domain.
tx_rst	in [0:0]		Bus m_axis_tx_s_axis_direct_tx_app_m_axis_direct_tx_app is synchronous to this reset signal.
rx_clk	in [0:0]		Bus s_axis_rx_s_axis_stat_s_axis_direct_rx_app_m_axis_direct_rx_app is synchronous to this clock domain.
rx_rst	in [0:0]		Bus s_axis_rx_s_axis_stat_s_axis_direct_rx_app_m_axis_direct_rx_app is synchronous to this reset signal.
ddr_clk	in [0:0]	DDR_ENABLE = 1	Bus m_axi_ddr_m_axi_ddr_app is synchronous to this clock domain.
ddr_rst	in [0:0]	DDR_ENABLE = 1	Bus m_axi_ddr_m_axi_ddr_app is synchronous to this reset signal.
ddr_status	in [0:0]	DDR_ENABLE = 1
hbm_clk	in [0:0]	HBM_ENABLE = 1	Bus m_axi_hbm_m_axi_hbm_app is synchronous to this clock domain.
hbm_rst	in [0:0]	HBM_ENABLE = 1	Bus m_axi_hbm_m_axi_hbm_app is synchronous to this reset signal.
hbm_status	in [0:0]	HBM_ENABLE = 1
ddr_status_app	out [0:0]	APP_ENABLE = 1 and  DDR_ENABLE = 1
hbm_status_app	out [0:0]	APP_ENABLE = 1 and  HBM_ENABLE = 1

Building

This IP uses Corundum NIC repository, which needs to be cloned alongside the HDL repository. Do a git checkout to the latest tested version (commit - 37f2607). When the 10G-based implementation (e.g., in case of K26) is used, apply the indicated patch.

~/workspace$

git clone https://github.com/ucsdsysnet/corundum.git

~/workspace$

cd corundum

~/workspace/corundum$

git checkout 37f2607

~/workspace/corundum$

cd hdl/library/corundum/corundum_core

~/workspace/corundum/hdl/library/corundum/corundum_core$

make

Publications

The following papers pertain to the Corundum source code:

• J- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, Corundum: An Open-Source 100-Gbps NIC, in FCCM’20. (FCCM Paper, FCCM Presentation)

• J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (Thesis)

References

• HDL IP core at library/corundum/corundum_core