Template Module

The {module name} is responsible for {brief description}.

Files

Name	Description
library/spi_engine/spi_engine_execution/spi_engine_execution.v	Verilog source for the peripheral.
library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl	TCL script to generate the Vivado IP-integrator project for the peripheral.

Configuration Parameters

Name	Description	Default Value	Choices/Range
DATA_WIDTH	Data width of the parallel SDI/SDO data interfaces.	8	From 8 to 256.
NUM_OF_SDI	Number of MISO lines.	1	From 1 to 8.

Signal and Interface Pins

m_ctrl

Physical Port	Logical Port	Direction	Dependency
m_cmd_ready	cmd_ready	in
m_cmd_valid	cmd_valid	out
m_cmd_data	cmd_data	out [15:0]
m_sdo_ready	sdo_ready	in
m_sdo_valid	sdo_valid	out
m_sdo_data	sdo_data	out [7:0]
m_sdi_ready	sdi_ready	out
m_sdi_valid	sdi_valid	in
m_sdi_data	sdi_data	in [7:0]
m_sync_ready	sync_ready	out
m_sync_valid	sync_valid	in
m_sync	sync_data	in [7:0]

s0_ctrl

Physical Port	Logical Port	Direction	Dependency
s0_cmd_ready	cmd_ready	out
s0_cmd_valid	cmd_valid	in
s0_cmd_data	cmd_data	in [15:0]
s0_sdo_ready	sdo_ready	out
s0_sdo_valid	sdo_valid	in
s0_sdo_data	sdo_data	in [7:0]
s0_sdi_ready	sdi_ready	in
s0_sdi_valid	sdi_valid	out
s0_sdi_data	sdi_data	out [7:0]
s0_sync_ready	sync_ready	in
s0_sync_valid	sync_valid	out
s0_sync	sync_data	out [7:0]

s1_ctrl

Physical Port	Logical Port	Direction	Dependency
s1_cmd_ready	cmd_ready	out
s1_cmd_valid	cmd_valid	in
s1_cmd_data	cmd_data	in [15:0]
s1_sdo_ready	sdo_ready	out
s1_sdo_valid	sdo_valid	in
s1_sdo_data	sdo_data	in [7:0]
s1_sdi_ready	sdi_ready	in
s1_sdi_valid	sdi_valid	out
s1_sdi_data	sdi_data	out [7:0]
s1_sync_ready	sync_ready	in
s1_sync_valid	sync_valid	out
s1_sync	sync_data	out [7:0]

Ports

Physical Port	Direction	Dependency	Description
clk	in		Buses m_ctrl, s0_ctrl, s1_ctrl are synchronous to this clock domain.
resetn	in		Buses m_ctrl, s0_ctrl, s1_ctrl are synchronous to this reset signal.

Theory of Operation

The {module name} module implements {brief description}.