AD9740-FMC HDL project

Overview

The AD9740, AD9742, AD9744 and AD9748 are wideband, 3G members of the TxDAC® series of high performance, low power CMOS, digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 14-, 12-, 10-, and 8-bit DACs, is specifically optimized for the transmit signal path of communication systems. All the devices share the same interface options, small outline package, and pinout. The AD9740, AD9742, AD9744 and AD9748 also provide an upward or downward component selection path based on performance, resolution and financial cost, offering exceptional AC and DC performance while supporting update rates up to 210 MSPS.

The EVAL-AD9740, EVAL-AD9742, EVAL-AD9744 and EVAL-AD9748 evaluation boards are FMC form-factor boards with FMC connector that is compatible to the Vita 57.1 standard. This board provides the user with the flexibility to operate the AD9740, AD9742, AD9744 and AD9748 in various configurations.

Output configurations include transformer-coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators with the onboard option to add a resistor network for proper load termination. Provisions are also made to operate the AD9740, AD9742, AD9744 and AD9748 with either the onboard clock source (ADF4351) or with external clock configuration.

Supported boards

Supported devices

Supported carriers

Evaluation board	Carrier	FMC slot
EVAL-AD9740	ZedBoard	FMC-LPC
EVAL-AD9742	ZedBoard	FMC-LPC
EVAL-AD9744	ZedBoard	FMC-LPC
EVAL-AD9748	ZedBoard	FMC-LPC

Block design

Warning

The VADJ for Zedboard must be set to 3.3V.

Block diagram

The data path and clock domains are depicted in the below diagram:

Clock architecture

The ADF4351 on the evaluation board generates a 250 MHz differential clock. In system_top.v, this clock is received by an IBUFGDS and then divided by 2 using a BUFR primitive, producing a 125 MHz logic clock. This 125 MHz clock drives both the AXI AD9740 DAC core (dac_clk) and the DMA FIFO read clock (fifo_rd_clk). The axi_ad9740 IP uses ODDR primitives to output two samples per clock cycle (DDR), achieving a 250 MSPS DAC update rate.

Configuration

The project supports four target devices selected via the DEVICE environment variable at build time:

DEVICE	DAC_RESOLUTION	Description
AD9748	8	8-bit DAC
AD9740	10	10-bit DAC
AD9742	12	12-bit DAC
AD9744 (default)	14	14-bit DAC

The AXI AD9740 IP is configured with:

Parameter	Value	Description
CLK_RATIO	2	DDR output, two samples per clock cycle
DDS_CORDIC_DW	22	CORDIC data width for higher DDS precision
DDS_CORDIC_PHASE_DW	22	CORDIC phase width for higher DDS precision

The AXI DMAC is configured with:

Parameter	Value	Description
DMA_DATA_WIDTH_SRC	64	Memory side data width (HP1 port)
DMA_DATA_WIDTH_DEST	32	DAC side data width (2 × 16-bit samples)
CYCLIC	1	Cyclic transfer support enabled

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq
ad9740_dac	0x44A7_0000
ad9740_dma	0x44A4_0000

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
ad9740_dma	13	57	89

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9740_fmc/zed

~/hdl/projects/ad9740_fmc/zed$

make

The default build targets the AD9744 (14-bit). To build for a different device, set the DEVICE environment variable:

~$

cd hdl/projects/ad9740_fmc/zed

~/hdl/projects/ad9740_fmc/zed$

make DEVICE=AD9740

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

EVAL-AD9740-FMC HDL project source code

IP name	Source code link	Documentation link
AXI_AD9740	library/axi_ad9740	AXI AD9740
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.