AD5529R HDL project

Overview

The AD5529R is a 16-channel, 16-bit voltage-output digital-to-analog converter (DAC) with an integrated 4.096V precision reference. The device supports programmable output ranges up to ±20V or 0-40V, making it suitable for industrial control, test and measurement, and process automation applications.

Key features include:

16-bit resolution across 16 channels
Built-in digital functions (toggle, dither, ramp)
Monitor multiplexer for diagnostics
SPI interface: 16-bit instruction + 8/16-bit data
Maximum SPI clock: 50 MHz
Settling time: 8-20 µs (range-dependent)

This HDL project implements the SPI Engine framework with DMA streaming, enabling SPI throughput of 123.4 kSPS per channel with hardware-triggered updates and zero CPU involvement. Actual update rate is settling-time limited (125 kSPS at 0-5V range, down to 50 kSPS at ±20V range).

Supported boards

EVAL-AD5529R-ARDZ

Supported devices

AD5529R

Supported carriers

Cora Z7-07S (XC7Z007S)

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at CPU/Memory interconnects addresses).

Instance	Zynq
spi_ad5529r_axi_regmap	0x44A0_0000
ad5529r_dma	0x44A4_0000
trig_gen	0x44B0_0000
axi_ad5529r_clkgen	0x44B1_0000
toggle_gen	0x44B2_0000
axi_sysid_0	0x4500_0000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	spi_ad5529r	ad5529r	0

GPIOs

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
ad5529r_clear	OUT	32	86
ad5529r_reset	OUT	33	87
ad5529r_alarm	IN	34	88

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
ad5529r_dma	13	57	89
spi_ad5529r/axi_regmap	12	56	88

Warning

IRQ_F2P mode is REVERSE (bit 15 = highest priority).

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad5529r/coraz7s

~/hdl/projects/ad5529r/coraz7s$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

ad5529r HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SYSID	library/axi_sysid	AXI System ID
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID

SPI Engine Framework documentation

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.