EVAL-AD9783

Dual 16-Bit / 14-Bit / 12-Bit LVDS Interface 500 MSPS DACs Evaluation Board.

Overview

The EVAL-AD9783 evaluation board allows users to easily set up and test the 72-lead lead frame chip scale package (LFCSP_VQ) of the AD9783 / AD9781 / AD9780 devices. Paying careful attention to layout and circuit design, combined with a prototyping area, allows the user to effectively evaluate the AD9783, AD9781, AD9780 in applications that require high resolution and high speed conversion.

Features:

• High dynamic range, dual DAC parts

• Low noise and intermodulation distortion

• Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF

• Innovative switching output stage permits usable outputs beyond Nyquist frequency

• LVDS inputs with dual-port or optional interleaved single-port operation

• Differential analog current outputs are programmable from 8.6 mA to 31.7 mA full scale

• Auxiliary 10-bit current DACs with source/sink capability for external offset nulling

Applications:

• Wireless infrastructure

• W-CDMA, CDMA2000, TD-SCDMA, WiMAX

• Wideband communications

• LMDS/MMDS, point-to-point

• RF signal generators, arbitrary waveform generators

Figure 1 EVAL-AD9783

Recommendations

People who follow the flow that is outlined have a much better experience with things. However, like many things, documentation is never as complete as it should be. If you have any questions, feel free to ask on our EngineerZone, but before that, please make sure you read our documentation thoroughly.

Table of contents

1. Using the evaluation board/full stack reference design that we offer:

   1. Prerequisites - what you need to get started

   2. Quick start guides:

      1. Using the ZCU102

   3. Linux Applications

      1. IIO Oscilloscope

      2. Scopy

2. Design with the AD9783 / AD9781 / AD9780

   • Block diagram

     • AD9783 product page

     • AD9781 product page

     • AD9780 product page

   • Resources for designing a custom AD9783-based platform:

     1. For Linux software:

        1. About the device driver:

           • AXI DAC HDL

     2. HDL reference design which you must use in your FPGA.

3. Help and Support

Block diagram

The AD9783-EBZ HDL project on the ZCU102 uses the AXI AD9783 IP core to interface the DAC via a parallel bus. The AXI-DMAC streams sample data from DDR memory to the IP core, which drives the AD9783 at up to 500 MSPS.

Figure 14 AD9780/AD9781/AD9783 functional block diagram.

ADI articles

1. AD9783 Product Page

2. AD9781 Product Page

3. AD9780 Product Page

Warning

All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection. Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.