EVAL-ADRV904x

Integrated 8T8R RF Transceiver with Digital Pre-Distortion and Crest Factor Reduction.

Overview

The EVAL-ADRV904x, is an FMC radio card designed to showcase the ADRV9040 and ADRV9044, highly integrated, radio frequency (RF) agile transceivers offering 8 independently controlled transmitters, 2 observation receiver inputs for monitoring transmitter channels, 8 independently controlled receivers, integrated local oscillator (LO) and clock synthesizers, digital front-end (DFE) with crest factor reduction (CFR) and digital pre-distortion (DPD), and digital signal processing functions providing a complete transceiver solution.

The device provides the high radio performance and low-power consumption demanded by cellular infrastructure applications and massive MIMO base stations, offering advanced DFE capabilities on an integrated ARM Cortex-A55 quad-core processor.

Features:

• Both chips feature:

  • 8 differential transmitters & 8 differential receivers

  • 2 differential observation receivers

  • Support for TDD and FDD applications

  • LO tunable range: 450 MHz to 7100 MHz

  • RF frequency bands:

    • Low Band (LB): 600 MHz to 2800 MHz

    • Mid Band (MB): 1.8 GHz to 4.8 GHz

    • High Band (HB): 4.5 GHz to 6 GHz

  • Integrated Digital Front-End (DFE) with CFR and digital pre-distortion

  • ARM Cortex-A55 quad-core processor for DFE algorithms (DPD, CLGC, VSWR)

  • JESD204B and JESD204C digital interface with fixed and floating-point data format support

  • Zero-IF (ZIF) architecture

• Complete ADRV9040/ADRV9044 radio cards for evaluation

  • FMC connector for FPGA integration

  • Fully integrated fractional-N RF synthesizer

  • Fully integrated clock synthesizer

Applications:

• 3G/4G/5G TDD and FDD massive MIMO

• Macro and small cell base stations

• Software defined radios

• Wireless infrastructure

Recommendations

People who follow the flow that is outlined, have a much better experience with things. However, like many things, documentation is never as complete as it should be. If you have any questions, check the Help and Support section at the bottom of the page.

To better understand the ADRV9040 / ADRV9044, we recommend to use the EVAL-ADRV904x evaluation board.

Table of contents

1. Using the evaluation board/full stack reference design that we offer:

   1. User guide

   2. Prerequisites - what you need to get started

   3. Quick start guides:

      1. Using the ZCU102 (ZynqMP)

   4. Configure an SD Card with Kuiper

   5. Linux Applications

      1. IIO Oscilloscope

2. Design with the ADRV9040/ADRV9044

   1. Block diagram

   1. ADRV9040 product page

   2. ADRV9044 product page

   3. Full data sheet and chip design package

   1. Hardware in the Loop / How to design your own custom BaseBand

   1. GNU Radio

   2. Transceiver Toolbox

   1. Resources for designing a custom ADRV9040/ADRV9044-based platform software

   1. For Linux software:

      1. About the device driver:

         1. JESD204B/C Link Transmit Peripheral / JESD204B Transmit Linux driver

         2. JESD204B/C Link Receive Peripheral / JESD204B Receive Linux driver

         3. AXI ADXCVR / AXI_ADXCVR High-speed transceivers Linux driver

         4. AXI ADC HDL Linux driver

         5. AXI DAC HDL Linux driver

         6. AD9528 Low Jitter Clock Generator Linux driver

         7. AXI DMAC / AXI-DMAC DMA Controller Linux driver

         8. ADRV904x Linux device driver

      2. About the device tree:

         1. Customizing the device tree on the target

      3. About the JESD204 utilities:

         1. JESD204 FSM

         2. JESD204 status utility

         3. JESD204 Eye Scan

         4. JESD204 Interface Framework

   2. Changing the VCXO frequency and updating the default RF Transceiver Profile

   3. HDL reference design which you must use in your FPGA.

3. Digital Pre-Distortion (DPD)

   1. ADRV904x DPD User Guide

   2. DPD Introduction

   3. DFE System Overview

   4. DPD Capabilities

   5. High Level Development Flow

   6. DPD Evaluation Prerequisites

   7. Evaluating ADRV904x DPD

   8. DPD Error Troubleshooting

   9. DPD Analysis Tool

4. SDR math

5. Help and Support

Block diagram

The ADRV9040/ADRV9044 features a zero-IF (ZIF) architecture that provides wide bandwidth with dynamic range suitable for contiguous and non-contiguous multicarrier applications. The transceiver includes:

1. 8 transmitter channels with integrated DACs and DPD/CFR

2. 8 receiver channels with integrated ADCs

3. 2 observation receiver channels for transmitter monitoring

4. Integrated RF and clock synthesizers

5. Integrated ARM Cortex-A55 quad-core processor for DFE

6. JESD204B/C digital interface

7. SPI control interface

8. General purpose I/O and interrupts

Videos

Software Defined Radio using the Linux IIO Framework

Video

http://ftp.fau.de/fosdem/2015/devroom-software_defined_radio/iiosdr.mp4

ADI articles

Four Quick Steps to Production: Using Model-Based Design for Software-Defined Radio:

1. Part 1

2. Part 2

3. Part 3

4. Part 4

About JESD standard:

1. JESD204B Survival Guide

2. Part 1

3. Part 2

MathWorks webinars

1. Modelling and Simulating Analog Devices’ RF Transceivers with MATLAB and SimRF

2. Getting Started with Software-Defined Radio using MATLAB and Simulink

Unboxing guide

Detailed description of the setup procedure for ADRV9009 (similar procedure for ADRV904x):

Detailed unboxing guide

Warning

All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection. Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.

Help and support

For questions and more information, please visit the Help and Support technical support community.