User guide
The complete user guide of the evaluation board can be found at ADRV904x Evaluation System User Guide (UG-2229).
Hardware guide
Power supply
The power supply comes from the FMC connector, given by the FPGA.
The VADJ values can be checked out in the README.md file of each combination with an FPGA, at: projects/adrv904x.
Schematic, PCB Layout, Bill of Materials
Design files for the EVAL-ADRV904x evaluation board include:
Schematics
PCB Layout
Bill of Materials
Design package
Please refer to the ADRV9040 product page for downloadable design files.
Software guide
The evaluation board is supported with the Libiio library. This library is cross-platform (Windows, Linux, Mac) with language bindings for C, C#, Python, MATLAB, and others. One easy to example that can be used with it is:
For details on how to customize the driver for a specific use case, see the ADRV904x driver customization guide.
Kernel configuration
To enable the ADRV904x driver when building the Linux kernel from source:
Device Drivers --->
Industrial I/O support --->
[*] Enable ring buffer support within IIO
[*] Industrial I/O lock free software ring
[*] Enable triggered sampling support
Analog to digital converters --->
<*> Analog Devices ADRV904X/ADRV9040 RF Transceiver driver
Frequency Synthesizers DDS/PLL --->
Direct Digital Synthesis --->
<*> Analog Devices CoreFPGA AXI DDS driver
<*> JESD204 High-Speed Serial Interface Support
Required firmware files
The ADRV904x Linux driver requires the following firmware files to be present
in /lib/firmware/ on the target system:
File |
Device tree property |
Description |
|---|---|---|
|
|
ARM processor firmware for calibrations and device configuration |
|
|
ARM Cortex-A55 firmware for DFE features (DPD, CLGC, VSWR) |
|
|
Stream processor image (user-generated via ADI evaluation software) |
|
|
Receiver gain table (default or custom) |
|
|
Device profile (user-generated configuration file) |
These files are included in the Kuiper Linux SD card image.
Note
The stream_image.bin must be regenerated when updating firmware
versions, as it is version-specific. The DeviceProfileTest.bin is
use-case specific and contains filter coefficients, clock rates, and DFE
resource settings.
Device variants
Two device tree configurations are provided:
Default profile (
zynqmp-zcu102-rev10-adrv904x.dts): Standard TX/RX configuration without observation receiver path activation.NLS profile (
zynqmp-zcu102-rev10-adrv904x-nls.dts): Enables the observation receiver (ORx) path for transmitter monitoring and DPD calibration.
To select the device tree, copy the corresponding system.dtb to the SD
card boot partition before powering up the board.
IIO attributes
The adrv904x-phy IIO device exposes sysfs attributes under
/sys/bus/iio/devices/iio:deviceN/. For a full attribute reference, see the
ADRV904x Linux device driver
wiki page.
Channel naming
IIO prefix |
Signal |
|---|---|
|
Main receivers RX1–RX8 |
|
Observation receiver ORx1 |
|
Observation receiver ORx2 |
|
Transmitters TX1–TX8 |
|
TRX LO1 |
|
TRX LO2 |
|
TRX AUX LO |
Local oscillator control
The two RF PLLs are tunable from 450 MHz to 7100 MHz. It is recommended to re-run the initial calibrations when crossing a divide-by-2 boundary.
~$
cat /sys/bus/iio/devices/iio:device1/out_altvoltage0_LO1_frequency
3765000000
~$
echo 3764000000 > /sys/bus/iio/devices/iio:device1/out_altvoltage0_LO1_frequency
RX channel attributes
Attribute |
Access |
Description |
|---|---|---|
|
Read/Write |
Enable (1) or disable (0) receiver channel N |
|
Read/Write |
Receiver hardware gain in dB (0 to 32 dB range, 256 gain settings) |
|
Read/Write |
Receiver RF bandwidth in Hz |
|
Read/Write |
Enable quadrature error correction tracking (0 or 1) |
|
Read/Write |
Enable baseband DC offset tracking calibration (0 or 1) |
~$
cat /sys/bus/iio/devices/iio:device1/in_voltage0_en
1
~$
echo 0 > /sys/bus/iio/devices/iio:device1/in_voltage0_en
TX channel attributes
Attribute |
Access |
Description |
|---|---|---|
|
Read/Write |
Enable (1) or disable (0) transmitter channel N |
|
Read/Write |
Transmitter attenuation in dB (range 0 to −32 dB, higher resolution via digital gain) |
|
Read/Write |
Transmitter RF bandwidth in Hz (baseband filter tunable 300–840 MHz) |
|
Read/Write |
Enable quadrature error correction tracking (0 or 1) |
|
Read/Write |
Enable LO leakage tracking calibration (0 or 1) |
~$
cat /sys/bus/iio/devices/iio:device1/out_voltage0_hardwaregain
-6.000000 dB
~$
echo -12 > /sys/bus/iio/devices/iio:device1/out_voltage0_hardwaregain
~$
cat /sys/bus/iio/devices/iio:device1/out_voltage0_rf_bandwidth
400000000
Temperature sensor
The device internal temperature is available via the in_temp0_input
attribute (value in milli-degrees Celsius):
~$
cat /sys/bus/iio/devices/iio:device1/in_temp0_input
72000
Debug facilities
Debug attributes are accessible via debugfs at
/sys/kernel/debug/iio/iio:deviceN/.
PRBS injection
bist_framer_0_prbs injects a data source into Framer 0 for JESD204 link
verification. Write the data source index to select it:
Value |
Data source |
|---|---|
|
ADC data |
|
Checkerboard |
|
Toggle 0/1 |
|
PRBS31 |
|
PRBS23 |
|
PRBS15 |
|
PRBS9 |
|
PRBS7 |
|
Ramp |
|
16-bit programmed pattern (repeat) |
|
16-bit programmed pattern (execute once) |
~$
echo 8 > /sys/kernel/debug/iio/iio:device1/bist_framer_0_prbs
Digital loopback
bist_framer_loopback routes the digital framer output directly to the
digital deframer input, bypassing the RF path:
Value |
Mode |
|---|---|
|
Disable loopback |
|
Digital framer → digital deframer |
~$
echo 1 > /sys/kernel/debug/iio/iio:device1/bist_framer_loopback
Tone injection
bist_tone injects a configurable NCO tone into the TX path. Syntax:
echo <enable> <frequency_Hz> <gain_index> > bist_tone
enable:
0= disable TX NCO,1= enable on all transmittersfrequency_Hz: tone frequency in Hz
gain_index:
Index |
NCO gain |
|---|---|
|
0 dB |
|
6 dB |
|
12 dB |
|
18 dB |
|
24 dB |
|
30 dB |
|
36 dB |
|
42 dB |
|
48 dB |
~$
echo 1 30000000 2 > /sys/kernel/debug/iio/iio:device1/bist_tone
Direct register access
direct_reg_access allows reading and writing individual device registers.
To access HDL core registers, set bit 31 of the address.
~$
echo 0x7 > /sys/kernel/debug/iio/iio:device1/direct_reg_access
~$
cat /sys/kernel/debug/iio/iio:device1/direct_reg_access
0x40
~$
echo 0x7 0x50 > /sys/kernel/debug/iio/iio:device1/direct_reg_access
~$
cat /sys/kernel/debug/iio/iio:device1/direct_reg_access
0x50
~$
echo 0x80000000 > /sys/kernel/debug/iio/iio:device1/direct_reg_access
~$
cat /sys/kernel/debug/iio/iio:device1/direct_reg_access
0x80062