User guide
The complete user guide of the evaluation board can be found at EVAL-AD4134FMCZ User Guide.
Additional documentation:
Hardware guide
Hardware configuration
The EVAL-AD4134FMCZ board connects to the FPGA carrier via the FMC LPC connector. On the ZedBoard, configure the BOOT switches (JP7-JP11) and the MIO0 jumper (JP6) for the desired boot mode. Refer to the ZED Quickstart guide for the specific jumper positions for SD card and JTAG boot modes.
The following jumpers on the evaluation board must be configured:
Jumper/Solder link |
Position |
Description |
|---|---|---|
JP16 |
Mounted |
MODE (Slave) and DCLKIO (Input) |
The device mode of operation can be set to either MASTER or SLAVE by changing the P10 jumper position:
P10 open: master mode (default on the EVB)
P10 shorted: slave mode
Make sure to change the mode in both software (app_config.h file) and
hardware, and power-cycle the EVAL-AD4134FMCZ to reflect the new mode.
Power supply
The EVAL-AD4134FMCZ evaluation board requires an external 9 V power supply connected to the appropriate header on the evaluation board.
The AD4134 can be powered from a 4.5 V to 5.5 V analog power supply and a 1.65 V to 1.95 V digital power supply for 1.8 V I/O level. It supports external voltage references of 2.5 V, 4.096 V, and 5 V, and a crystal or CMOS external clock of 48 MHz.
The FPGA carrier board (ZedBoard) is powered separately through its own 12 V power input connector (J20). The VADJ voltage provided from the carrier through the FMC connector must be set to 1.8 V as specified in the HDL project’s README at AD4134-FMC HDL project.
Analog inputs
The AD4134 provides 4 differential analog input channels with simultaneous sampling at up to 1496 kSPS. The device uses continuous-time sigma-delta modulation technology that does not use sample-and-hold circuitry, providing inherent alias rejection up to 100 dB. The maximum input bandwidth is 391.5 kHz.
For testing purposes, connect a signal generator to the analog inputs of the evaluation board using the appropriate jumper wires or SMB connectors. For optimal performance, use a low noise, low distortion signal source such as an Audio Precision audio analyzer.
Data acquisition performance (SPI clock and sample rate)
The system is designed to acquire continuous data from the 24-bit 4-channel precision alias free ADC device, supporting a maximum sample rate of 1496 kSPS. The HDL reference design operates in slave mode, with both the data clock (DCLK) and output data rate (ODR) signals generated by the FPGA using the SPI Engine Framework.
Schematic, PCB layout, bill of materials
Design and layout files for the evaluation board can be found on the product page:
Software guide
The evaluation board is supported both with Linux (using the Libiio library) and with no-OS (bare metal). The Libiio library is cross-platform (Windows, Linux, Mac) with language bindings for C, C#, Python, and others. Applications that can be used with it are:
Python support is available through the pyadi-iio library.