User guide

The complete user guide of the evaluation board can be found at EVAL-AD7134FMCZ User Guide.

Additional documentation:

AD7134 Data Sheet

Hardware guide

Hardware configuration

The EVAL-AD7134FMCZ board connects to the FPGA carrier via the FMC LPC connector. On the ZedBoard, configure the BOOT switches (JP7-JP11) and the MIO0 jumper (JP6) for the desired boot mode. Refer to the ZED Quickstart guide for the specific jumper positions for SD card and JTAG boot modes.

The following jumpers on the evaluation board must be configured:

Jumper/Solder link	Position	Description
JP14	Mounted	DEC0/DCLKIO
JP15	Mounted	DEC0/DCLKIO
JP16	Mounted	MODE
JP17	Mounted	MODE

The device mode of operation can be set to either MASTER or SLAVE by changing the P10 jumper position:

P10 open: master mode (default on the EVB)
P10 shorted: slave mode

Make sure to change the mode in both software (app_config.h file) and hardware, and power-cycle the EVAL-AD7134FMCZ to reflect the new mode.

Power supply

The EVAL-AD7134FMCZ evaluation board requires an external 9 V power supply connected to the appropriate header on the evaluation board.

The AD7134 can be powered from a 4.5 V to 5.5 V analog power supply and a 1.65 V to 1.95 V digital power supply for 1.8 V I/O level. It supports external voltage references of 2.5 V, 4.096 V, and 5 V, and a crystal or CMOS external clock of 48 MHz.

The FPGA carrier board (ZedBoard) is powered separately through its own 12 V power input connector (J20). The VADJ voltage provided from the carrier through the FMC connector must be set to 1.8 V as specified in the HDL project’s README at AD7134-FMC HDL project.

Analog inputs

The AD7134 provides 4 differential analog input channels with simultaneous sampling at up to 1.5 MSPS. The device uses continuous-time sigma-delta modulation technology that does not use sample-and-hold circuitry, providing inherent alias rejection up to 100 dB.

For testing purposes, connect a signal generator to the analog inputs of the evaluation board using the appropriate jumper wires or SMB connectors. For optimal performance, use a low noise, low distortion signal source such as an Audio Precision audio analyzer.

Data acquisition performance

The AD7134 supports a wide range of output data rate (ODR) frequencies, from 0.01 kSPS to 1496 kSPS with less than 0.01 SPS adjustment resolution, allowing the user to granularly vary sampling speed to achieve coherent sampling.

The device offers three digital filter profile options:

Filter type	ODR range
Wideband low ripple	2.5 kSPS to 374 kSPS
Sinc3 (fast responding)	0.01 kSPS to 1496 kSPS
Sinc6 (balanced)	2.5 kSPS to 1.496 MSPS

The HDL reference design uses the SPI Engine to interface with the ADC. The design operates in slave mode, with both the data clock (DCLK) and output data rate (ODR) signals generated by the FPGA.

Schematic, PCB layout, bill of materials

Design and layout files for the evaluation board can be found on the product page:

EVAL-AD7134FMCZ design files

Software guide

The evaluation board is supported both with Linux (using the Libiio library) and with no-OS (bare metal). The Libiio library is cross-platform (Windows, Linux, Mac) with language bindings for C, C#, Python, and others. Applications that can be used with it are:

For no-OS (bare metal), the AD7134 IIO firmware application runs on the SDP-K1 (MBED) or Nucleo-L552ZEQ (STM32) controller boards and communicates over UART or VirtualCOM port. The firmware supports SPI and TDM communication modes, with continuous and burst data capture. Refer to the no-OS quick start section for details.

Python support is available through the pyadi-iio library using the ad7134_data_capture.py script.