User guide

Warning

The AD-FMCADC3-EBZ is a legacy product and is no longer actively supported. This documentation is provided for reference only.

Hardware guide

Revision A

The revision A board has the amplifier gain control via SPI. When powering up the FMCADC3 board, the gain of the amplifier will default to an attenuated state. When applying a signal source to the FMCADC3 at the analog input connector J201, use a low jitter, low noise signal source with a level at -20 dBm. Apply a signal source no greater than -8 dBm when achieving full-scale of the converter and maximum gain of the amplifier is applied.

Specifications

The AD-FMCADC3-EBZ board’s primary purpose is to quickly and easily connect to an FMC carrier platform and start collecting data using the AD9625. The board is designed to be easy to use. Out of the box the board will self power and self clock when connected to an FMC carrier. The only other required equipment is your chosen signal source to provide an input signal to “Ain”.

This rapid prototyping board also has 4 vertically mounted SMA connectors. These are labeled SYSREF IN and SYSREF OUT. These are to enable synchronization of multiple AD-FMCADC3-EBZ boards together using characteristics of the JESD204B high speed serial interface between the AD9625 and FPGA.

Clocking

The AD-FMCADC3-EBZ provides multiple options for clocking the AD9625. The default configuration of the board clocks the ADC using an on-board 2.5 GHz, low noise, crystal oscillator from Crystek. This oscillator is then routed through a wide band transformer producing the differential clock for the ADC. Alternatively, the oscillator can be disconnected and an external clock source connected by only changing two components on the board. A single ended clock connected to the CLK+ input would then be routed through the transformer in the same way.

Finally, the option exists to connect a differential clock to the board using both the CLK+ and CLK- inputs. Then referencing the schematic make the component changes to directly route the differential input bypassing the transformer.

Front End

The AD-FMCADC3-EBZ uses a passive front end designed for very wide bandwidth. A single ended input needs to be provided to “Ain”. A 1:2 impedance ratio broadband balun then converts the input signal differentially to the ADA4961 inputs and has a 1.6 GHz bandwidth at -3 dB.

Software guide

FPGA Code

The AD-FMCADC2-EBZ and the AD-FMCADC3-EBZ use common HDL. Library cores used:

Linux

Help & Support

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