User guide

Warning

The AD-FMCADC4-EBZ is a legacy product that has been retired and is no longer available for sale. It has been removed from the HDL and software repositories, but is still available in the git history. This documentation is provided for reference only.

Hardware guide

The AD-FMCADC4-EBZ board’s primary purpose is to demonstrate the capabilities of the devices on board quickly and easily by providing a seamless interface to an FMC carrier platform and running the reference design on the carrier FPGA. The board is designed to self power and self clock when connected to the FMC carrier. The analog signals (up to four) are connected to J301A, J301B, J301C and J301D. This rapid prototyping board can also be synchronized across channels.

Clocking

The AD-FMCADC4-EBZ includes an on-board 80 MHz reference oscillator from Crystek. This feature can be disconnected and an external reference can be applied through J901. When referencing the schematic make sure the proper component changes are made in order to directly route the input into the AD9528.

Analog Front End

The AD-FMCADC4-EBZ uses a passive front end designed for very wide bandwidth. A single ended input needs to be provided to the analog inputs mentioned earlier. A 1:2 impedance ratio broadband balun then converts the input signal differentially to the ADA4961 inputs and has a 1.6 GHz bandwidth at -3 dB. Each channel amplifier can be adjusted independently in terms of gain.

Revision A

The revision A board supports amplifier gain control via SPI. After power-up, the gain of the amplifier defaults to an attenuated state. Use a low jitter, low noise signal source with a level at -20 dBm to the analog inputs (J301-A/B/C/D). Apply a signal source no greater than -10 dBm to achieve full-scale of the converter when maximum gain of the amplifier is applied.

Software guide

FPGA Code

The AD-FMCADC4-EBZ HDL project has been removed from the repository but is still available in the git history. Library cores previously used:

• axi_adxcvr

• axi_clkgen

• axi_dmac

• axi_hdmi_tx

• axi_jesd204_rx

• axi_spdif_tx

• axi_sysid

• jesd204_rx

• sysid_rom

• util_adcfifo

Note

ILA was supported in reference designs prior to the hdl_2016_r1 release.

Figure 1 FMCADC4 ILA plot screen capture

Linux

• AD9680 AXI Linux driver

• ADA4961 Low Distortion, 3.2 GHz, RF DGA Linux driver

• JESD204B/C Receive Linux driver

• JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux driver

• ZC706 Linux image

Help & Support

Hint

• The HDL user guide contains all the documentation, build instructions and register map tables.

• The following quick links allow you to browse the GitHub repository: library components and projects.

• Questions? We can help with FPGA questions, Linux driver questions, No-OS Drivers questions.